Page History

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1. Xilinx Zynq-7000 all programmable SoC, U5
2. System Controller CPLD, U26
3. Programmable quad clock generator , U10
4. 10/100/1000 Mbps Ethernet PHY, U7
5. 2 x 4-Gbit DDR3L SDRAM (1.35 V), U12 and U13
6. Hi-speed USB 2.0 ULPI transceiver, U6
7a. B2B connector Samtec Razor Beam™ LSHM-150, JM1
7b. B2B connector Samtec Razor Beam™ LSHM-150, JM2
7c. B2B connector Samtec Razor Beam™ LSHM-130, JM3
8. 32-MByte quad SPI Flash memory, U14
9. Low-power RTC with battery backed SRAM, U16
10. 4A PowerSoC DC-DC converter, U1
11. Green LED (DONE), D2
12. Red LED (SC), D3
13. Green LED (MIO7), D4
14. 2-bit bidirectional 1-MHz I²C bus voltage-level translator, U20

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Bank	Type	B2B Connector	I/O Signal Count	Voltage	Notes
13	HR	JM1	48	User	Supported voltages Allowed voltage level from 1.2V to 3.3V.
34	HR/HP	JM2	18	User	On TE0715-xx-15 has no HP banks modules, banks 34 and 35 are HR banks on this module!Banks 34 and 35 on , allowed voltage level from 1.2V to 3.3V. On TE0715-xx-30 are HP banks and support voltages modules, banks 34 and 35 are HP banks, allowed voltage level from 1.2V to 1.8V.
35	HR/HP	JM2	50	User	As above.
34	HR/HP	JM3	16	User	As above.
500	MIO	JM1	8	3.3V	-
501	MIO	JM1	6	1.8V	-
112	GT	JM3	4 lanes	N/A -	See also next section MGT Lanes.
112	GT CLK	JM3	1 differential input	N/A	NB! AC coupling capacitors required on baseboard requiredcarrier board.

Table 3: General overview of board to board I/O signals.

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connector connection and FPGA pins Zynq SoC pin connection:

Lane	Bank	Type	Signal Name	B2B PinFPGA	Zynq SoC Pin
0	112	GTX	MGT_RX0_P MGT_RX0_N MGT_TX0_P MGT_TX0_N	JM3-10 JM3-8 JM3-9 JM3-7	MGTXRXP0_112, AA7 MGTXRXN0_112, AB7 MGTXTXP0_112, AA3 MGTXTXN0_112, AB3
1	112	GTX	MGT_RX1_P MGT_RX1_N MGT_TX1_P MGT_TX1_N	JM3-16 JM3-14 JM3-15 JM3-13	MGTXRXP1_112, W8 MGTXRXN1_112, Y8 MGTXTXP1_112, W4 MGTXTXN1_112, Y4
2	112	GTX	MGT_RX2_P MGT_RX2_N MGT_TX2_P MGT_TX2_N	JM3-22 JM3-20 JM3-21 JM3-19	MGTXRXP2_112, AA9 MGTXRXN2_112, AB9 MGTXTXP2_112, AA5 MGTXTXN2_112, AB5
3	112	GTX	MGT_RX3_P MGT_RX3_N MGT_TX3_P MGT_TX3_N	JM3-28 JM3-26 JM3-27 JM3-25	MGTXRXP3_112, W6 MGTXRXN3_112, Y6 MGTXTXP3_112, W2 MGTXTXN3_112, Y2

Table 4: MGT lanes overview.

Below are listed MGT banks bank reference clock sources.

Clock signal	Bank	Source	FPGA Pin	Notes
MGT_CLK0_P	112	B2B, JM3-33	MGTREFCLK0P_112, U9	Supplied by the carrier board.
MGT_CLK0_N	112	B2B, JM3-31	MGTREFCLK0N_112, V9	Supplied by the carrier board.
MGT_CLK1_P	112	U10, CLK2A	MGTREFCLK1P_112, U5	On-board Si5338A.
MGT_CLK1_N	112	U10, CLK2B	MGTREFCLK1N_112, V5	On-board Si5338A.

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JTAG Signal	B2B Connector Pin
TMS	JM2-93
TDI	JM2-95
TDO	JM2-97
TCK	JM2-99

Table 6: MGT lanes JTAG interface signals.

Note
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation.

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