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title	Figure 1: TE0807-02 03 block diagram

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Main Components

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title	Figure 2: TE0807-02 03 main components

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Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

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Bank	Type	Lane	Signal Name	B2B Pin	FPGA Pin
224	GTH	0	B224_RX0_P B224_RX0_N B224_TX0_P B224_TX0_N	J1-69 J1-71 J1-68 J1-70	MGTHRXP0_224, V2 MGTHRXN0_224, V1 MGTHTXP0_224, W4 MGTHTXN0_224, W3
		1	B224_RX1_P B224_RX1_N B224_TX1_P B224_TX1_N	J1-63 J1-65 J1-62 J1-64	MGTHRXP1_224, U4 MGTHRXN1_224, U3 MGTHTXP1_224, V6 MGTHTXN1_224, V5
		2	B224_RX2_P B224_RX2_N B224_TX2_P B224_TX2_N	J1-57 J1-59 J1-56 J1-58	MGTHRXP2_224, T2 MGTHRXN2_224, T1 MGTHTXP2_224, T6 MGTHTXN2_224, T5
		3	B224_RX3_P B224_RX3_N B224_TX3_P B224_TX3_N	J1-51 J1-53 J1-50 J1-52	MGTHRXP3_224, P2 MGTHRXN3_224, P1 MGTHTXP3_224, R4 MGTHTXN3_224, R3
225	GTH	0	B225_RX0_P B225_RX0_N B225_TX0_P B225_TX0_N	J1-45 J1-47 J1-44 J1-46	MGTHRXP0_225, N4 MGTHRXN0_225, N3 MGTHTXP0_225, P6 MGTHTXN0_225, P5
		1	B225_RX1_P B225_RX1_N B225_TX1_P B225_TX1_N	J1-39 J1-41 J1-38 J1-40	MGTHRXP1_225, M2 MGTHRXN1_225, M1 MGTHTXP1_225, M6 MGTHTXN1_225, M5
		2	B225_RX2_P B225_RX2_N B225_TX2_P B225_TX2_N	J1-33 J1-35 J1-32 J1-34	MGTHRXP2_225, K2 MGTHRXN2_225, K1 MGTHTXP2_225, L4 MGTHTXN2_225, L3
		3	B225_RX3_P B225_RX3_N B225_TX3_P B225_TX3_N	J1-27 J1-29 J1-26 J1-28	MGTHRXP3_225, J4 MGTHRXN3_225, J3 MGTHTXP3_225, K6 MGTHTXN3_225, K5
226	GTH	0	B226_RX0_P B226_RX0_N B226_TX0_P B226_TX0_N	J1-21 J1-23 J1-20 J1-22	MGTHRXP0_226, H2 MGTHRXN0_226, H1 MGTHTXP0_226, H6 MGTHTXN0_226, H5
		1	B226_RX1_P B226_RX1_N B226_TX1_P B226_TX1_N	J1-15 J1-17 J1-14 J1-16	MGTHRXP1_226, G4 MGTHRXN1_226, G3 MGTHTXP1_226 G8 MGTHTXN1_226, G7
		2	B226_RX2_P B226_RX2_N B226_TX2_P B226_TX2_N	J1-9 J1-11 J1-8 J1-10	MGTHRXP2_226, F2 MGTHRXN2_226, F1 MGTHTXP2_226, F6 MGTHTXN2_226, F5
		3	B226_RX3_P B226_RX3_N B226_TX3_P B226_TX3_N	J1-3 J1-5 J1-2 J1-4	MGTHRXP3_226, E4 MGTHRXN3_226, E3 MGTHTXP3_226, E8 MGTHTXN3_226, E7
227	GTH	0	B227_TX0_P B227_TX0_N B227_RX0_P B227_RX0_N	J2-45 J2-43 J2-48 J2-46	MGTHRXP0MGTHTXP0_227, D1D6 MGTHRXN0MGTHTXN0_227, D2D5MGTHTXP0 MGTHRXP0_227, D5D2 MGTHTXN0MGTHRXN0_227, D6D1
		1	B227_TX1_P B227_TX1_N B227_RX1_P B227_RX1_N	J2-39 J2-37 J2-42 J2-40	MGTHRXP1MGTHTXP1_227, C3C8 MGTHRXN1MGTHTXN1_227, C4C7MGTHTXP1 MGTHRXP1_227, C7C4 MGTHTXN1MGTHRXN1_227, C8C3
		2	B227_TX2_P B227_TX2_N B227_RX2_P B227_RX2_N	J2-33 J2-31 J2-36 J2-34	MGTHRXP2MGTHTXP2_227, B1B6 MGTHRXN2MGTHTXN2_227, B2B5MGTHTXP2 MGTHRXP2_227, B5B2 MGTHTXN2MGTHRXN2_227, B6B1
		3	B227_TX3_P B227_TX3_N B227_RX3_P B227_RX3_N	J2-27 J2-25 J2-30 J2-28	MGTHRXP3MGTHTXP3_227, A3A8 MGTHRXN3MGTHTXN3_227, A4A7MGTHTXP3 MGTHRXP3_227, A7A4 MGTHTXN3MGTHRXN3_227, A8A3
505	GTR	0	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	J2-69 J2-67 J2-72 J2-70	PS_MGTRRXP0MGTRTXP0_505, M27 PS_MGTRRXN0MGTRTXN0_505, M28 PS_MGTRTXP0MGTRRXP0_505, L29 PS_MGTRTXN0MGTRRXN0_505, L30
		1	B505_TX1_P B505_TX1_N B505_RX1_P B505_RX1_N	J2-63 J2-61 J2-66 J2-64	PS_MGTRRXP1MGTRTXP1_505, K27 PS_MGTRRXN1MGTRTXN1_505, K28 PS_MGTRTXP1MGTRRXP1_505, J29 PS_MGTRTXN1MGTRRXN1_505, J30
		2	B505_TX2_P B505_TX2_N B505_RX2_P B505_RX2_N	J2-57 J2-55 J2-60 J2-58	PS_MGTRRXP2MGTRTXP2_505, J25 PS_MGTRRXN2MGTRTXN2_505, J26 PS_MGTRTXP2MGTRRXP2_505, H27 PS_MGTRTXN2MGTRRXN2_505, H28
		3	B505_TX3_P B505_TX3_N B505_RX3_P B505_RX3_N	J2-51 J2-49 J2-54 J2-52	PS_MGTRRXP3MGTRTXP3_505, G25 PS_MGTRRXN3MGTRTXN3_505, G26 PS_MGTRTXP3MGTRRXP3_505, G29 PS_MGTRTXN3MGTRRXN3_505, G30

Table 5: MGT lanes

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PS MIO	Function	Connected to
0	SPI0	U7-B2, CLK
1	SPI0	U7-D2, DO/IO1
2	SPI0	U7-C4, WP/IO2
3	SPI0	U7-D4, HOLD/IO3
4	SPI0	U7-D3, DI/IO0
5	SPI0	U7-C2, CS
6	N/A	Not connected
7	SPI1	U17-C2, CS
8	SPI1	U17-D3, DI/IO0
9	SPI1	U17-D2, DO/IO1
10	SPI1	U17-C4, WP/IO2
11	SPI1	U17-D4, HOLD/IO3
12	SPI1	U17-B2, CLK
13 ... 77	user dependent	B2B connector J2

Table 11: TE0807-02 03 PS MIO mapping

On-board Peripherals

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Table 12: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-02 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.

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title	Figure 4: TE0807-02 03 Power-on Sequence Diagram

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Power Rail Name	B2B J1 Pins	B2B J2 Pins	B2B J3 Pins	B2B J4 Pins	Directions	Note
PL_DCIN	151, 153, 155, 157, 159	-	-	-	Input	-
DCDCIN	-	154, 156, 158, 160, 153, 155, 157, 159	-	-	Input	-
LP_DCDC	-	138, 140, 142, 144	-	-	Input	-
PS_BATT	-	125	-	-	Input	-
GT_DCDC	-	-	157, 158, 159, 160	-	Input	-
PLL_3V3	-	-	152	-	Input	U5 (programmable PLL) 3.3V nominal input
SI_PLL_1V8	-	-	151	-	Output	Internal voltage level 1.8V nominal output
PS_1V8	-	99	147, 148	-	Output	Internal voltage level 1.8V nominal output
PL_1V8	91, 121	-	-	-	Output	Internal voltage level 1.8V nominal output
DDR_1V2	-	135	-	-	Output	Internal voltage level 1.2V nominal output
VCCO47	-	-	43, 44	-	Input	-
VCCO48	-	-	15, 16	-	Input	-
VCCO64	-	-	-	58, 106	Input	-
VCCO65	-	-	-	69, 105	Input	-
VCCO66	90, 120	-	-	-	Input	-

Table 19: TE0807-02 03 power rails

Bank Voltages

Bank	Type	Schematic Name	Voltage	Reference Input Voltage	Voltage Range
47	HD	VCCO47	user	-	1.2V to 3.3V
48	HD	VCCO48	user	-	1.2V to 3.3V
64	HP	VCCO64	user	VREF_64, pin J4-88	1.2V to 1.8V
65	HP	VCCO65	user	VREF_65, pin J4-15	1.2V to 1.8V
66	HP	VCCO66	user	VREF_66, pin J1-108	1.2V to 1.8V
500	MIO	PS_1V8	1.8V	-	-
501	MIO	PS_1V8	1.8V	-	-
502	MIO	PS_1V8	1.8V	-	-
503	CONFIG	PS_1V8	1.8V	-	-

Table 20: TE0807-02 03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

Include Page

	DRAFT:5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B ConnectorsDRAFT:
	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	-0.3	74	V	TPS82085SIL / EN63A0QI data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN	-0.3	74	V	TPS82085SIL / TPS51206 data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC	-0.3	4	V	TPS3106K33DBVR data sheet
GT_DCDC	-0.3	74	V	TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT	-0.5	2	V	Xilinx DS925 data sheet
PLL_3V3	-0.5	3.8	V	Si5345/44/42 data sheet
VCCO for HD I/O banks	-0.5	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	-0.5	2	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.5	VCCO_PSIO + 0.55	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage	-0.5	1.1	V	Xilinx document DS925
PS GTR absolute input voltage	-0.5	1.1	V	Xilinx document DS925
MGT clock absolute input voltage	-0.5	1.3	V	Xilinx document DS925
MGT Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.5	1.2	V	Xilinx DS925 data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	-0.5	VCC + 0.5	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41	-0.3	VDD + 0.3	V	TPS3106 data sheet, VDD = LP_DCDC
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD)	-0.3	7	V	TPS82085SIL data sheet
Storage temperature (ambient)	-40	100	°C	ROHM Semiconductor SML-P11 Series data sheet

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	3.3	3.6	V	EN63A0QI / TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN	3.3	3.6	V	TPS82085SIL / TPS51206PSQ data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC	3.3	3.6	V	TPS82085SIL / TPS3106 data sheet
GT_DCDC	3.3	3.6	V	TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_PS_BATT	1.2	1.5	V	Xilinx DS925 data sheet
PLL_3V3	3.3	3.47	V	Si5345/44/42 data sheet 3.3V typical
VCCO for HD I/O banks	1.14	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	0.95	1.9	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks.	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.2	VCCO_PSIO + 0.2	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
PL bank reference voltage VREF pin	-0.5	2	V	Xilinx DS925 data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	0	VCC	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pin 'MR' of TPS3106K33DBVR Voltage Monitor, U41	0	VDD	V	TPS3106 data sheet, VDD = LP_DCDC

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Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

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Date	Revision	Notes	PCN Link	Documentation Link
2020-06-05	03	current available module revision	PCN-20200511	TE0807-03
-	02	current available module revision	-	TE0807-02
-	01	first production release	-	TE0807-01

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Aug 2018

Date

Revision

Contributors

Description

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	modified-date
	modified-date
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Correction on MGT Lanes (column "FPGA Pin" of bank 227 and 505 was incorrect)

2021-09-07

v.28

John Hartfiel

Correction on Power section

2021-06-10

v.27

John Hartfiel

correction number IOs in BD

2021-05-17

v.26

John Hartfiel

typo correction in DDR section

2021-05-03

v.25

Martin Rohrmüller

Updated to REV03

2021-03-11

v.24

Antti Lukats

Corrected B2B include macro

2019-06-14

v.22

John Hartfiel

typo correction SI5345 I2C address
typo B2B Pin of CLK signals

2018-08-07

v.20

Ali Naseri

initial document

Table 24: Document change history

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Trenz Electronic Documentation

Versions Compared

Old Version 22

New Version Current

Key

Main Components

On-board Peripherals

DDR4 SDRAM

Bank Voltages

Board to Board Connectors

Document Change History