Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Title
anchorFigure_1
titleFigure 1: TE0807-02 03 block diagram


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision68
diagramNameTE0807-01 block diagram
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth642641


Scroll Only


Main Components

Scroll Title
anchorFigure_2
titleFigure 2: TE0807-02 03 main components


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision23
diagramNameTE0807-02 main components
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


Scroll Only


...

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

...

BankTypeLaneSignal NameB2B PinFPGA Pin
224GTH0
  • B224_RX0_P
  • B224_RX0_N
  • B224_TX0_P
  • B224_TX0_N
  • J1-69
  • J1-71
  • J1-68
  • J1-70
  • MGTHRXP0_224, V2
  • MGTHRXN0_224, V1
  • MGTHTXP0_224, W4
  • MGTHTXN0_224, W3
1
  • B224_RX1_P
  • B224_RX1_N
  • B224_TX1_P
  • B224_TX1_N
  • J1-63
  • J1-65
  • J1-62
  • J1-64
  • MGTHRXP1_224, U4
  • MGTHRXN1_224, U3
  • MGTHTXP1_224, V6
  • MGTHTXN1_224, V5
2
  • B224_RX2_P
  • B224_RX2_N
  • B224_TX2_P
  • B224_TX2_N
  • J1-57
  • J1-59
  • J1-56
  • J1-58
  • MGTHRXP2_224, T2
  • MGTHRXN2_224, T1
  • MGTHTXP2_224, T6
  • MGTHTXN2_224, T5
3
  • B224_RX3_P
  • B224_RX3_N
  • B224_TX3_P
  • B224_TX3_N
  • J1-51
  • J1-53
  • J1-50
  • J1-52
  • MGTHRXP3_224, P2
  • MGTHRXN3_224, P1
  • MGTHTXP3_224, R4
  • MGTHTXN3_224, R3
225GTH0
  • B225_RX0_P
  • B225_RX0_N
  • B225_TX0_P
  • B225_TX0_N
  • J1-45
  • J1-47
  • J1-44
  • J1-46
  • MGTHRXP0_225, N4
  • MGTHRXN0_225, N3
  • MGTHTXP0_225, P6
  • MGTHTXN0_225, P5
1
  • B225_RX1_P
  • B225_RX1_N
  • B225_TX1_P
  • B225_TX1_N
  • J1-39
  • J1-41
  • J1-38
  • J1-40
  • MGTHRXP1_225, M2
  • MGTHRXN1_225, M1
  • MGTHTXP1_225, M6
  • MGTHTXN1_225, M5
2
  • B225_RX2_P
  • B225_RX2_N
  • B225_TX2_P
  • B225_TX2_N
  • J1-33
  • J1-35
  • J1-32
  • J1-34
  • MGTHRXP2_225, K2
  • MGTHRXN2_225, K1
  • MGTHTXP2_225, L4
  • MGTHTXN2_225, L3
3
  • B225_RX3_P
  • B225_RX3_N
  • B225_TX3_P
  • B225_TX3_N
  • J1-27
  • J1-29
  • J1-26
  • J1-28
  • MGTHRXP3_225, J4
  • MGTHRXN3_225, J3
  • MGTHTXP3_225, K6
  • MGTHTXN3_225, K5
226GTH0
  • B226_RX0_P
  • B226_RX0_N
  • B226_TX0_P
  • B226_TX0_N
  • J1-21
  • J1-23
  • J1-20
  • J1-22
  • MGTHRXP0_226, H2
  • MGTHRXN0_226, H1
  • MGTHTXP0_226, H6
  • MGTHTXN0_226, H5
1
  • B226_RX1_P
  • B226_RX1_N
  • B226_TX1_P
  • B226_TX1_N
  • J1-15
  • J1-17
  • J1-14
  • J1-16
  • MGTHRXP1_226, G4
  • MGTHRXN1_226, G3
  • MGTHTXP1_226 G8
  • MGTHTXN1_226, G7
2
  • B226_RX2_P
  • B226_RX2_N
  • B226_TX2_P
  • B226_TX2_N
  • J1-9
  • J1-11
  • J1-8
  • J1-10
  • MGTHRXP2_226, F2
  • MGTHRXN2_226, F1
  • MGTHTXP2_226, F6
  • MGTHTXN2_226, F5
3
  • B226_RX3_P
  • B226_RX3_N
  • B226_TX3_P
  • B226_TX3_N
  • J1-3
  • J1-5
  • J1-2
  • J1-4
  • MGTHRXP3_226, E4
  • MGTHRXN3_226, E3
  • MGTHTXP3_226, E8
  • MGTHTXN3_226, E7
227GTH0
  • B227_TX0_P
  • B227_TX0_N
  • B227_RX0_P
  • B227_RX0_N
  • J2-45
  • J2-43
  • J2-48
  • J2-46
  • MGTHRXP0MGTHTXP0_227, D1D6
  • MGTHRXN0MGTHTXN0_227, D2D5MGTHTXP0
  • MGTHRXP0_227, D5D2
  • MGTHTXN0MGTHRXN0_227, D6D1
1
  • B227_TX1_P
  • B227_TX1_N
  • B227_RX1_P
  • B227_RX1_N
  • J2-39
  • J2-37
  • J2-42
  • J2-40
  • MGTHRXP1MGTHTXP1_227, C3C8
  • MGTHRXN1MGTHTXN1_227, C4C7MGTHTXP1
  • MGTHRXP1_227, C7C4
  • MGTHTXN1MGTHRXN1_227, C8C3
2
  • B227_TX2_P
  • B227_TX2_N
  • B227_RX2_P
  • B227_RX2_N
  • J2-33
  • J2-31
  • J2-36
  • J2-34
  • MGTHRXP2MGTHTXP2_227, B1B6
  • MGTHRXN2MGTHTXN2_227, B2B5MGTHTXP2
  • MGTHRXP2_227, B5B2
  • MGTHTXN2MGTHRXN2_227, B6B1
3
  • B227_TX3_P
  • B227_TX3_N
  • B227_RX3_P
  • B227_RX3_N
  • J2-27
  • J2-25
  • J2-30
  • J2-28
  • MGTHRXP3MGTHTXP3_227, A3A8
  • MGTHRXN3MGTHTXN3_227, A4A7MGTHTXP3
  • MGTHRXP3_227, A7A4
  • MGTHTXN3MGTHRXN3_227, A8A3
505GTR0
  • B505_TX0_P
  • B505_TX0_N
  • B505_RX0_P
  • B505_RX0_N
  • J2-69
  • J2-67
  • J2-72
  • J2-70
  • PS_MGTRRXP0MGTRTXP0_505, M27
  • PS_MGTRRXN0MGTRTXN0_505, M28
  • PS_MGTRTXP0MGTRRXP0_505, L29
  • PS_MGTRTXN0MGTRRXN0_505, L30
1
  • B505_TX1_P
  • B505_TX1_N
  • B505_RX1_P
  • B505_RX1_N
  • J2-63
  • J2-61
  • J2-66
  • J2-64
  • PS_MGTRRXP1MGTRTXP1_505, K27
  • PS_MGTRRXN1MGTRTXN1_505, K28
  • PS_MGTRTXP1MGTRRXP1_505, J29
  • PS_MGTRTXN1MGTRRXN1_505, J30
2
  • B505_TX2_P
  • B505_TX2_N
  • B505_RX2_P
  • B505_RX2_N
  • J2-57
  • J2-55
  • J2-60
  • J2-58
  • PS_MGTRRXP2MGTRTXP2_505, J25
  • PS_MGTRRXN2MGTRTXN2_505, J26
  • PS_MGTRTXP2MGTRRXP2_505, H27
  • PS_MGTRTXN2MGTRRXN2_505, H28
3
  • B505_TX3_P
  • B505_TX3_N
  • B505_RX3_P
  • B505_RX3_N
  • J2-51
  • J2-49
  • J2-54
  • J2-52
  • PS_MGTRRXP3MGTRTXP3_505, G25
  • PS_MGTRRXN3MGTRTXN3_505, G26
  • PS_MGTRTXP3MGTRRXP3_505, G29
  • PS_MGTRTXN3MGTRRXN3_505, G30

Table 5: MGT lanes

...

PS MIOFunctionConnected to
0SPI0U7-B2, CLK
1SPI0U7-D2, DO/IO1
2SPI0U7-C4, WP/IO2
3SPI0U7-D4, HOLD/IO3
4SPI0U7-D3, DI/IO0 
5SPI0 U7-C2, CS
6N/ANot connected
7SPI1U17-C2, CS
8SPI1U17-D3, DI/IO0
9SPI1U17-D2, DO/IO1
10SPI1U17-C4, WP/IO2
11SPI1U17-D4, HOLD/IO3
12SPI1U17-B2, CLK
13 ... 77user dependentB2B connector J2

Table 11: TE0807-02 03 PS MIO mapping

On-board Peripherals

...

Table 12: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-02 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.

...

Scroll Title
anchorFigure_3
titleFigure 3: TE0807-02 03 Power Distribution Diagram


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision1
diagramNameTE0807 power distribution diagram
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth642


Scroll Only


...

Scroll Title
anchorFigure_4
titleFigure 4: TE0807-02 03 Power-on Sequence Diagram


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision2
diagramNameTE0807 Power-On Sequence Diagram
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth648


Scroll Only


...

Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins

Directions

Note
PL_DCIN151, 153, 155, 157, 159---Input-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

--Input-
LP_DCDC-138, 140, 142, 144--Input-
PS_BATT-125--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-135--Output

Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-

Table 19: TE0807-02 03 power rails

Bank Voltages

BankTypeSchematic NameVoltageReference Input VoltageVoltage Range
47HDVCCO47user-1.2V to 3.3V
48HDVCCO48user-1.2V to 3.3V
64HPVCCO64userVREF_64, pin J4-881.2V to 1.8V
65HPVCCO65userVREF_65, pin J4-151.2V to 1.8V
66HPVCCO66userVREF_66, pin J1-1081.2V to 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 20: TE0807-02 03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

...

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.374VTPS82085SIL / EN63A0QI data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN-0.374VTPS82085SIL / TPS51206 data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.374VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925
MGT clock absolute input voltage-0.51.3VXilinx document DS925

MGT Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
(EN_PLL_PWR, EN_LPD)
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet

...

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN3.33.6VEN63A0QI / TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN3.33.6VTPS82085SIL / TPS51206PSQ data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC3.33.6VTPS82085SIL / TPS3106 data sheet
GT_DCDC3.33.6VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATTPS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.33.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
PL bank reference voltage VREF pin-0.52VXilinx DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

...

  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 4mm5mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

...

DateRevision

Notes

PCN LinkDocumentation Link
2020-06-0503current available module revisionPCN-20200511TE0807-03
-02current available module revision-TE0807-02
-01first production release-TE0807-01

...

Scroll Title
anchorFigure_7
titleFigure 7: Module hardware revision number
draw.io Diagram
bordertrue
diagramNameTE0807-03_HRN
simpleViewerfalse
width
linksauto
tbstyletop
lboxtrue
diagramWidth180
revision1
Image Removed


Document Change History

HTML
<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

...

Jun 2019 Aug 2018

Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Correction on MGT Lanes (column "FPGA Pin" of bank 227 and 505 was incorrect)

2021-09-07

  • Correction on Power section
2021-06-10v.27John Hartfiel
  • correction number IOs in BD
2021-05-17v.26John Hartfiel
  • typo correction in DDR section
2021-05-03v.25Martin Rohrmüller
  • Updated to REV03

2021-03-11

v.24

Antti Lukats

  • Corrected B2B include macro

2019-06-14

v.22John Hartfiel
  • typo correction SI5345 I2C address
  • typo B2B Pin of CLK signals

2018-08-07

v.20Ali Naseri
  • initial document

Table 24: Document change history

...