Page History

...

• MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
• Memory
  - 64bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/Os
  - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
  - Serial transceivers: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DC-DC regulators and 13 LDOs
  - LP, FPLPD, FPD, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin

...

Main Components

...

Table 3: Selectable boot modes by dedicated boot mode pins.

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

...

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

...

Table 45: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board, and clock inputs are also . The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Table 56: MGT reference clock sources

...

Table 47: B2B connector pin-out of JTAG interface.

...

Table 58: B2B connector pin-out of MPSoC's PS configuration bank.

...

Table 69: B2B connector pin-out of analog input pins

...

Table 710: PS MIO pin assignment of the Quad SPI Flash memory ICs.

...

Table 8: TE0807-01 PS MIO mapping

On-board Peripherals

Flash

Table 11: TE0807-03 PS MIO mapping

On-board Peripherals

Flash

The TE0807 The TE0808 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 1012: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-01 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit 64bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

...

Table 11: Programmable PLL clock generator input/outputTable 13: Programmable PLL clock generator input/output.

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 1214: B2B connector pin-out of Si5345A programmable clock generator.

...

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Table 15: On-board osciallators

MAC Address EEPROMs

There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I²C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL)Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

Table 1416: LED's description.

Power and Power-On Sequence

...

Table 1517: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808 TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

...

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-04 TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

...

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages::

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

...

Operation Conditions of the DC-DC Converter Control Signals

...

Table 1618: Recommended operation conditions of DC-DC converter control signals.

...

Power Rails

Table 1619: TE0807-01 03 power rails

Bank Voltages

Table 1720: TE0807-01 03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

...

Table 1821: Module absolute maximum ratings

...

Table 1922: Recommended operating conditions

...

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm5mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

...

Table 2023: Hardware revision history table

...

Document Change History

<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

...

Date

...

Revision

...

Contributors

...

Description

...

...

 be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Table 24

...

• initial document

Table 21: Document change history

Disclaimer

...