Page History
Template Revision 2.6 - on construction
...
HTML |
---|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
...
hidden | true |
---|---|
id | Comments |
Important General Note:
...
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
...
Figure template (note: inner scroll ignore/only only with drawIO object):
...
anchor | Figure_xyz |
---|---|
title | Text |
Scroll Ignore |
---|
Create DrawIO object here: Attention if you copy from other page, use |
Scroll Only |
---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
...
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
...
anchor | Table_xyz |
---|---|
title | Text |
...
Scroll pdf ignore | ||||
---|---|---|---|---|
Table of contents
|
Overview
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.
Key Features
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Excerpt |
---|
|
Revision History
...
- add every update file on the download
- add design changes on description
...
anchor | Table_DRH |
---|---|
title | Design Revision History |
...
...
...
- TE Script update
- rework of the FSBLs
- some additional Linux features
- MAC from EEPROM
...
- Rework Board Part Files (PS)
- small design changes
- SI5338 reconfiguration default activated on FSBL
- update linux startup app
...
- new assembly variant
...
- Board Part Bug fix with UART 1
...
- No Design changes
- Add FSBL for Flash Programming
...
...
...
...
...
- New Web Link on Board Part Files
- Add optional FSBL Code to reprogram SI5338
...
...
...
...
...
...
...
...
...
...
- changed Flash typ on TE0715_board_files.csv
(older one is not supported on Vivado 2017.2)
...
...
...
...
...
...
...
...
...
- initial release
Release Notes and Know Issues
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
anchor | Table_KI |
---|---|
title | Known Issues |
...
Requirements
Software
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
anchor | Table_SW |
---|---|
title | Software |
...
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
anchor | Table_HWM |
---|---|
title | Hardware Modules |
...
Design supports following carriers:
...
...
...
...
...
...
Additional HW Requirements:
...
anchor | Table_AHW |
---|---|
title | Additional Hardware |
...
Content
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
...
anchor | Table_DS |
---|---|
title | Design sources |
...
Additional Sources
...
anchor | Table_ADS |
---|---|
title | Additional design sources |
...
Prebuilt
...
hidden | true |
---|---|
id | Comments |
Notes :
...
anchor | Table_PF |
---|---|
title | Prebuilt files |
...
File
...
File-Extension
...
Description
...
Debian SD-Image
...
*.img
...
Debian Image for SD-Card
...
MCS-File
...
*.mcs
...
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
...
MMI-File
...
*.mmi
...
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
...
SREC-File
...
*.srec
...
Converted Software Application for MicroBlaze Processor Systems
...
anchor | Table_PF |
---|---|
title | Prebuilt files (only on ZIP with prebult content) |
...
File
...
File-Extension
...
Description
...
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
...
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Note: Select correct one, see TE Board Part Files
...
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
...
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
...
- prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
...
Launch
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch. TE0715-0x-30-xx only: HP IO Banks max power supply voltage is 1.8V. |
Programming
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0715" possible - Copy image.ub on SD-Card
- Set Boot Mode to QSPI-Boot and insered SD.
- Depends on Carrier, see carrier TRM.
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
- Webserver to get access to Zynq
Vivado HW Manager
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Monitoring:
- Si5338 CLKS:
- Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
- MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL → 50MHz on delivered configuration, see FSBL description).
- Si5338 CLKS:
Scroll Title | ||||
---|---|---|---|---|
| ||||
System Design - Vivado
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Block Design
Scroll Title | ||||
---|---|---|---|---|
| ||||
PS Interfaces
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Activated interfaces:
...
...
...
Constrains
Basic module constrains
Code Block | ||||
---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
Code Block | ||||
---|---|---|---|---|
| ||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Code Block | ||||
---|---|---|---|---|
| ||||
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]] |
Code Block | ||||
---|---|---|---|---|
| ||||
# for fmeter only
# set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
# set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
# set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/BUFG_O[0]}] |
Software Design - SDK/HSI
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:
Application
...
hidden | true |
---|---|
id | Comments |
----------------------------------------------------------
FPGA Example
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2018.3 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11
TE modified 2018.3 xilisf_v5_11
- Changed default Flash type to 5.
----------------------------------------------------------
Zynq Example:
zynq_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example:
----------------------------------------------------------
zynqmp_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
...
...
General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- SI5338 Configuration
zynq_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0715
Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
...
language | js |
---|
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Device Tree
...
language | js |
---|
...
...
...
...
...
...
...
...
...
...
...
Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_RTC_DRV_ISL12022=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_usbutils=y
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Page properties | ||||
---|---|---|---|---|
| ||||
Note: |
SI5338
File location <design name>/misc/Si5338/Si5338-*.slabtimeproj
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties | ||||
---|---|---|---|---|
| ||||
|
...
anchor | Table_dch |
---|---|
title | Document change history. |
...
Authors
...
Page info | ||||||||
---|---|---|---|---|---|---|---|---|
|
...