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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
Date | Version | Changes | Author |
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2023-02-08 | 3.1.12 | - removed content of
- Special FSBL for QSPI programming
| ma | 2022-08-24 | 3.1.11 | - Modification from link "available short link"
| ma | 2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1.9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | | ma |
| 3.1.3 | | ma |
| 3.1.2 | minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.src description added USB for programming
| ma |
| 3.1.1 | swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | |
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| 3.0 | |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro ...
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Overview
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scroll-office | true |
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - Add basic key features, which can be tested with the design
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Excerpt |
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- Vitis/Vivado 2022.2
- PetaLinux
- SD
- ETH
- MAC from EEPROM
- USB
- I2C
- RTC
- FMeter
- Modified FSBL (some additional outputs and SI5338 reconfiguration)
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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title | Design Revision History |
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Date | Vivado | Project Built | Authors | Description |
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2023-07-05 | 2022.2 | TE0715-test_board-vivado_2022.2-build_2_20230705115102.zip TE0715-test_board_noprebuilt-vivado_2022.2-build_2_20230705115102.zip | Waldemar Hanemann | | 2023-05-06 | 2021.2.1 | TE0715-test_board-vivado_2021.2-build_20_20230506205024.zip TE0715-test_board_noprebuilt-vivado_2021.2-build_20_20230506205024.zip | Manuela Strücker | | 2022-02-09 | 2021.2 | TE0715-test_board-vivado_2021.2-build_11_20220208131345.zip TE0715-test_board_noprebuilt-vivado_2021.2-build_11_20220208131345.zip | Manuela Strücker | | 2021-12-16 | 2020.2 | TE0715-test_board-vivado_2020.2-build_9_20211216124925.zip TE0715-test_board_noprebuilt-vivado_2020.2-build_9_20211216124901.zip | Manuela Strücker | | 2021-06-16 | 2020.2 | TE0715-test_board-vivado_2020.2-build_5_20210611100936.zip TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210611100742.zip | Manuela Strücker | - update mount function (from busybox to util-linux 2.34)
| 2021-05-31 | 2020.2 | TE0715-test_board-vivado_2020.2-build_5_20210531083131.zip TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210531083148.zip | John Hartfiel/ Manuela Strücker | - bugfix TE0715_board_files.csv for TE0715-04-71I33-L ID
| 2021-04-27 | 2020.2 | TE0715-test_board-vivado_2020.2-build_5_20210428094945.zip TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210428095209.zip
| John Hartfiel/ Manuela Strücker | - update to vivado version 2020.2
- implemented boot.scr file for distro_boot
| 2020-06-10 | 2019.2 | TE0715-test_board-vivado_2019.2-build_12_20200610070857.zip TE0715-test_board_noprebuilt-vivado_2019.2-build_12_20200610071014.zip | John Hartfiel | - bugfix usb reset
- changes device tree for eeprom mac
- new variants
| 2019-05-09 | 2018.3 | TE0715-test_board-vivado_2018.3-build_05_20190509094447.zip TE0715-test_board_noprebuilt-vivado_2018.3-build_05_20190509094505.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- some additional Linux features
- MAC from EEPROM
| 2018-10-01 | 2018.2 | TE0715-test_board-vivado_2018.2-build_03_20181001131411.zip TE0715-test_board_noprebuilt-vivado_2018.2-build_03_20181001131421.zip | John Hartfiel | - Rework Board Part Files (PS)
- small design changes
- SI5338 reconfiguration default activated on FSBL
- update linux startup app
| 2018-04-26 | 2017.4 | TE0715-test_board-vivado_2017.4-build_07_20180426171530.zip TE0715-test_board_noprebuilt-vivado_2017.4-build_07_20180426171546.zip | John Hartfiel | | 2018-03-27 | 2017.4 | te0715-test_board-vivado_2017.4-build_07_20180327223552.zip te0715-test_board_noprebuilt-vivado_2017.4-build_07_20180327223606.zip | John Hartfiel | - Board Part Bug fix with UART 1
| 2018-01-05 | 2017.4 | te0715-test_board-vivado_2017.4-build_01_20180105195436.zip te0715-test_board_noprebuilt-vivado_2017.4-build_01_20180105195452.zip | John Hartfiel | - No Design changes
- Add FSBL for Flash Programming
| 2017-11-10 | 2017.2 | te0715-test_board-vivado_2017.2-build_05_20171110134232.zip te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip | John Hartfiel | - New Web Link on Board Part Files
- Add optional FSBL Code to reprogram SI5338
| 2017-10-19 | 2017.2 | te0715-test_board-vivado_2017.2-build_04_20171019141808.zip te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip | John Hartfiel | - changed Flash typ on TE0715_board_files.csv
(older one is not supported on Vivado 2017.2)
| 2017-09-22 | 2017.2 | te0715-test_board-vivado_2017.2-build_02_20170927143412.zip te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip | John Hartfiel | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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anchor | Table_KI |
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title-alignment | center |
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title | Known Issues |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Issues | Description | Workaround | To be fixed version |
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Wrong DDR Size on the preset files for Single core variants only | TE0715_12S_1C\1.1\preset.xml did not include DDR settings and board automation select wrong DDR size in this case. | open TE0715_12S_1C\1.1\preset.xml and add this parameter Code Block |
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<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/> |
| (will be done with 23.2 update) | QSPI Flash | Programming QSPI fails with Vivado 2021.2 and 2022.2 | use Vivado 2020.2 or 2019.2 or older for programming |
| Timing problems with Frequency counter | can be ignored | --- | with 2018-10-01 update |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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title | Software |
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Software | Version | Note |
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Vitis | 2022.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2022.2 | needed | SI ClockBuilder Pro | --- | optional |
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Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on
TE Board Part Files.Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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anchor | Table_HWM |
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title-alignment | center |
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title | Hardware Modules |
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orientation | portrait |
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cellHighlighting | true |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0715-02-15-1C | 03_15_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-02-15-1I | 03_15_1i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-02-15-1I1 | 03_15_1i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-02-30-1C | 03_30_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-02-30-1I | 03_30_1i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-03-15-1I | 03_15_1i_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-15-1I3 | 03_15_1i_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-15-2I | 03_15_2i_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-30-1C | 03_30_1c_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-30-1I | 03_30_1i_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-30-1I3 | 03_30_1i_1gb | REV03 | 1GB | 32MB | NA | NA | NA | TE0715-03-30-3E | 03_30_3e_1gb | REV03|REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0715-04-12S-1C | 04_12s_1c_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-15-1I | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-15-1I3 | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR 2.5mm connector | TE0715-04-15-1IC | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. 3M NOVEC coating | TE0715-04-15-2I* | 04_15_2i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-21C33-A | 04_12s_1c_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-30-1C | 04_30_1c_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-30-1I | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-30-1I3 | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. 2.5mm connector | TE0715-04-30-1IA | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. Micron Flash | TE0715-04-30-3E | 04_30_3e_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-51I33-A | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-51I33-AN | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. 3M NOVEC coating | TE0715-04-51I33-L | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR 2.5mm connector | TE0715-04-52I33-A | 04_15_2i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-71C33-A | 04_30_1c_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-71I33-A | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-71I33-L | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. 2.5mm connector | TE0715-04-73E33-A | 04_30_3e_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-30-1IY | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR, without RTC | TE0715-04-51I33-AY | 04_15_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR, without RTC | TE0715-04-52I33-AY | 04_15_2i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR, without RTC | TE0715-04-71C33-AY | 04_30_1c_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR, without RTC | TE0715-04-71I33-AY | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR, without RTC | TE0715-04-71I33-LY | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | Low Power DDR. 2.5mm connector, without RTC | TE0715-04-S003 | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | CAO: Low Power DDR | TE0715-05-51I33-AN | 04_15_1i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR. 3M NOVEC coating | TE0715-05-71C33-A | 04_30_1c_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-04-S015 | 04_30_1i_1gb | REV04 | 1GB | 32MB | NA | NA | CAO and Low Power DDR | TE0715-05-52I33-A | 04_15_2i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-21C33-A | 04_12s_1c_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-51I33-A | 04_15_1i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-71I33-A | 04_30_1i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-71I33-L | 04_30_1i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR. 2.5mm connector | TE0715-05-S002C1 | 04_15_2i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-51I33-L | 04_15_1i_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR 2.5mm connector | TE0715-05-73E33-A | 04_30_3e_1gb | REV05 | 1GB | 32MB | NA | NA | Low Power DDR | TE0715-05-S003C1 | 04_15_2i_1gb | REV05 | 1GB | 32MB | NA | NA | CAO:Low Power DDR |
*used as reference |
Design supports following carriers:
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anchor | Table_HWC |
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title-alignment | center |
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title | Hardware Carrier |
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orientation | portrait |
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Carrier Model | Notes |
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TE0701 |
| TE0703* |
| TE0705 |
| TE0706 |
| TEBA0841-02 |
|
*used as reference |
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
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Additional Sources
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anchor | Table_ADS |
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title-alignment | center |
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title | Additional design sources |
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orientation | portrait |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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SI5338 | <project folder>\misc\Si5338 | SI5338 Project with current PLL Configuration | init.sh | <project folder>\misc\sd\ | Additional Initialization Script for Linux (working from sd card only) |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title | Prebuilt files |
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orientation | portrait |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of AMD Software for the same Project.
Reference Design is available on:
Design Flow
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scroll-html | true |
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on AMD Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by AMD Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block |
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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|
------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from AMD Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
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"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
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This step depends on AMD Device/Hardware for Zynq-7000 series - copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze |
Generate Programming Files with Vitis
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") |
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TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
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TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Launch
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Programming
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Note:- Programming and Startup procedure
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
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TE0715-0x-30-xx only: HP IO Banks max power supply voltage is 1.8V. |
AMD documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select Create and open delivery binary folder
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Optional for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs BOOT.bin on QSPI flash) |
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TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0715 (optional) |
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- optional: use startup script init.sh for SD
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
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Note: See TRM of the Carrier, which is used. |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr |
Power On PCB
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1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
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This step depends on AMD Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
... |
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
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Win OS, see device manager, Linux OS see dmesg | grep tty (UART is *USB1) |
Linux Console:
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Note: Wait until Linux boot finished |
You can use Linux shell now.
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language | bash |
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theme | Midnight |
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i2cdetect -y -r 0 (check I2C 1 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).- Monitoring:
- Si5338 CLKs:
- Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
- MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optionally possible over FSBL → 50MHz on delivered configuration, see FSBL description).
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title | Vivado Hardware Manager |
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System Design - Vivado
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Block Design
draw.io Diagram |
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border | true |
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diagramName | BlockDiagram_TE0715_interactive |
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simpleViewer | false |
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width | 600 |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 2308 |
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revision | 3 |
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PS Interfaces
Activated interfaces:
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anchor | Table_PSI |
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title-alignment | center |
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title | PS Interfaces |
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orientation | portrait |
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Type | Note |
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DDR | --- | QSPI | MIO | I2C1 | MIO | UART0 | MIO | GPIO | MIO | ETH, USB Rst | MIO | SD0 | MIO | USB0 | MIO | ETH0 | MIO | TTC0..1 | EMIO | SWDT | EMIO |
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Constraints
Basic module constraints
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language | ruby |
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title | _i_bitgen_common.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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language | ruby |
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title | _i_unused_io.xdc |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constraints
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language | ruby |
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title | _i_io.xdc |
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set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]] |
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language | ruby |
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title | _i_timing.xdc |
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# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks mgt_clk1_clk_p]
set_false_path -from [get_clocks mgt_clk1_clk_p] -to [get_clocks clk_fpga_0] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2021.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
---------------------------------------------------------- ZynqMP Example: zynqmp_fsblTE modified 2021.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware.
---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
fsbl
TE modified 2022.2 FSBL
General:
Module Specific:
- Add Files: all TE Files start with te_*
fsbl_flash
TE modified 2022.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0715
Hello TE0715 is a AMD Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_NOWHERE=y
- CONFIG_ENV_OVERWRITE=y (used to overwrite environment parameter)
- CONFIG_ENV_IS_IN_FAT=y (needed to boot from SD card)
- CONFIG_ENV_IS_IN_SPI_FLASH=y (needed to boot from QSPI flash)
- # CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x1920000 (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)
- CONFIG_ZYNQ_MAC_IN_EEPROM=y
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50
Device Tree (system-user.dtsi in device-tree and uboot-device-tree)
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/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};
/*------------------- default --------------------*/
/*------------------ QSPI PHY --------------------*/
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/*--------------------- ETH PHY ------------------*/
&gem0 {
status = "okay";
ethernet_phy0: ethernet-phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
};
};
/*---------------------- USB PHY -----------------*/
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
//compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/*---------------------- I2C ---------------------*/
// i2c PLL: 0x70, i2c eeprom: 0x50
&i2c1 {
rtc@6F { // Real Time Clock
compatible = "isl12022";
reg = <0x6F>;
};
eeprom: eeprom@50 { //MAC EEPROM
compatible = "atmel,24c08";
reg = <0x50>;
};
};
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FSBL patch
Must be add manually --> work in progress
Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_RTC_DRV_ISL12022=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_usbutils=y
- CONFIG_util-linux-umount=y (uses mount/umount function from util-linux instead of busybox)
- CONFIG_util-linux-mount=y
- CONFIG_auto-login=y
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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SI5338
File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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title-alignment | center |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Date | Document Revision | Authors | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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infoType | Modified by |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| - Add Note for Single Core Variants to the Issue List
| | | | | 2023-05-08 | v.41 | Manuela Strücker | | 2022-02-09 | v.40 | Manuela Strücker | | 2021-12-16 | v.39 | Manuela Strücker | | 2021-06-16 | v.38 | Manuela Strücker | - changed mount/umount function in PetaLinux
| 2021-05-31 | v.37 | John Hartfiel | - Design update (bugfix csv file)
| | v.36 | Manuela Strücker | - Release 2020.2
- added boot.scr for distro boot
| 2020-06-10 | v.33 | John Hartfiel | | 2019-05-09 | v.32 | John Hartfiel | - Release 2018.3
- FSBL Rework
- Script rework
- some optional features
| 2018-10-01 | v.31 | John Hartfiel | - Release 2018.2
- Redesign Board Part Files
- New activate SI5338 example over FSBL
- small Design changes
- Update Documentation Style
| | v.30 | John Hartfiel | | | v.29 | John Hartfiel | | 2018-02-13 | v.28 | John Hartfiel | | 2017-11-10 | v.22 | John Hartfiel | - Design Update with new options
- Add Si5338 section
- Update FSBL section
| 2017-10-19 | v.21 | John Hartfiel | | 2017-10-19 | v.20 | John Hartfiel | | 2017-10-06 | v.18 | John Hartfiel | - Text correction
- Update Launch section
- Supported PCBs
| 2017-10-02 | v.14 | John Hartfiel | - Document update on Prebuilt section
| 2017-09-28 | v.13 | John Hartfiel | | -- | all | Page info |
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infoType | Modified users |
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| -- |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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