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Table of Contents

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#FTDI
Channel A		FTDI
Channel B		Pins A to GNotes
1JTAG/SPI (MPSSE)UARTJTAG, UARTJTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE
2JTAG/SPI (MPSSE)JTAG/SPI (MPSSE)JTAG, JTAGDual JTAG, only Channel A is Xilinx compatible
3UARTUARTUART, UARTDual UART
4I2CUARTI2C, UART 
5MPSSE 
8x GPIO 
6 
UART8x GPIO 
7UARTUARTnot usedUART to UART loopback
8not usedFast Serial 
FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode
9CPLD update onlynot useduser definedStandalone Module with CPLD and 8 user programmable I/O

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Signal J2 Pin NameJ2 Pin Name Signal
GND
1*GND
User DefinedCAUser Defined
VIO 

VDD 3.3V
User DefinedDBUser Defined
User DefinedFEUser Defined
User DefinedHGUser Defined / Button (Reset_n)

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI

GND-
1*-GND
ADBUS0TCK (output from adapter)
CAupUART RXD (input to adapter)BDBUS1 

VIO- 

-VDD 3.3V
ADBUS2TDO (input to adapter)upDB
UART TXD (output from adapter)BDBUS0
ADBUS1TDI (output from adapter)
FEdownLED
ADBUS3TMS (output from adapter)
HGupButton (Reset_n)

Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI

GND-
1*-GND
ADBUS0TCK (output from adapter)
CA
UART TXD (output from adapter)BDBUS0 

VIO- 

-VDD 3.3V
ADBUS2TDO (input to adapter)upDB upUART RXD (input to adapter)BDBUS1
ADBUS1TDI (output from adapter)
FEdownLED
ADBUS3TMS (output from adapter) 
HGupButton (Reset_n)

Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2

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FTDISignalPull up/down J2 Pin Name J2 Pin NamePull up/downSignalFTDI

GND-
1*-GND
BDBUS1UART RXD (input to adapter)upCA
TCK (output from adapter)ADBUS0 

VIO- 

-VDD 3.3 V
BDBUS0UART TXD (output from adapter)
DB
TMS (output from adapter)ADBUS3
ADBUS1TDI (output from adapter)
FEupTDO (input to adapter)ADBUS2 

not used
HG
CPLD User LED 'ULED'

Table 6: Pin header J2 signal assignment with DIPFORTy firmware.

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The DIP-switch S2 is to set different modes of powering the on-board peripherals and their components, the I/O supply voltages .Further functionalities are to secure the EEPROM content and to enable configuring programming the SC adapter board CPLD by JTAG interface:

S2ONOFFDefaultDescription
1Normal modeModule Adapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

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S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO sourced by and 3.3V source by base (Pin 5 and Pin 6 and drive Pin 5are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (3.3V (pin 5) and VIO (pin 6) sourced USB

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(Pin 5 and Pin 6 are shorted and both are 3.3V)

  • *max. 100mA for external components (It's not recommended to supply FPGA Module)
      Attention: Do not use this setting, if base power supply is connected to this pins!  For more details see Power supply of the adapter board  section.
  • **view of XMOD

Table 8: DIP-switch S2 power setting description.

User Push Button

The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.

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Date

Revision

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Description

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • update some link and change history

2018-01-18

v.37John Hartfiel
  • DIP-Switch description
2017-11-16

v.34

Page info
modified-datemodified-datedateFormatAli Naseri
  • Updated Power supply, DIP-Switch and CPLD section

2017-10-26

v.27

John Hartfiel
  • Update 2x6 Pin Header Figure 3
  • Update Links
2017-10-19

v.26

Ali Naseri
  • Initial document
--all


Page info
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Table 15: Document change history.

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