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Table of Contents
Overview
The Trenz Electronic TE0790 is an universal USB2.0 to JTAG, UART and GPIO adapter based on the FTDI FT2232H USB2 IC. The adapter board converts signals from USB2.0 to standard serial or parallel interfaces of Embedded Systems like JTAG, SPI, I²C and UART.
The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.
In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).
Following table describes the possible operation modes of the TE0790 adapter board. The operation modes are determined by the configuration of the FT2232H (done by programing the Configuration EEPROM) and the firmware implementation of the System Controller CPLD:
| # | FTDI Channel A | FTDI Channel B | Pins A to G | Notes |
|---|---|---|---|---|
| 1 | JTAG/SPI (MPSSE) | UART | JTAG, UART | JTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE |
| 2 | JTAG/SPI (MPSSE) | JTAG/SPI (MPSSE) | JTAG, JTAG | Dual JTAG, only Channel A is Xilinx compatible |
| 3 | UART | UART | UART, UART | Dual UART |
| 4 | I2C | UART | I2C, UART | |
| 5 | MPSSE | 8x GPIO | ||
| 6 | UART | 8x GPIO | ||
| 7 | UART | UART | not used | UART to UART loopback |
| 8 | not used | Fast Serial | FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode | |
| 9 | CPLD update only | not used | user defined | Standalone Module with CPLD and 8 user programmable I/O |
Table 1: Initial delivery state of programmable devices on the module.
MPSSE - FTDI protocol that is used by JTAG and SPI adapters based on FTDI devices.
Important notice on TE0790-xx variants:
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
Key Features
- Xmod form-factor
- size: 20 x 25 mm
- M3 mounting hole
- FT2232H
- USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
- Entire USB protocol handled on the chip
- USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
- USB2.0 to UART conversion
- Channel B UART RX/TX LED's
- Mini-USB B connector (more rigid then micro-USB)
- 93C56 EEPROM
- Lattice XO2-256 CPLD
- on board programmable using Lattice tools
- 8 universal I/O pins
- VCCIO either 3.3V or user supplied (1.8 to 3.3V)
- RED user LED
- 12 MHz clock from on-board Oscillator
- Variable power supply of the XMOD adapter board
- by Mini USB2.0 connector
- by base-board through pin header J2
- GREEN Power-on LED
- User button
- 4 position DIP switch
- Choose CPLD program mode
- FTDI EEPROM disable (not implemented in PCB REV 1)
- Use VIO same as VCC
- Use VCC from USB
Block Diagram
Figure 1: TE0790-02 block diagram.
Main Components
Figure 2: TE0790-02 main components.
- FTDI FT2232H IC U4
- 2x6 Pin Header (2.54mm, female), J2
- Mini USB B Connector J4
- Microchip 93AA56BT-I/OT Configuration EEPROM, U10
- DIP-switch S2
- Push button S1
- Lattice Semiconductor LCMXO2-256HC System Controller CPLD, U1
- SiTime SiT8008AI-73 oscillator @12MHz, U6
- Green LED, D1 (Power)
- Red LED, D4 (User)
- Red LED, D3 (UART RX)
- Red LED, D2 (UART TX)
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
| Configuration EEPROM U10 | variant depending | only programmed on TE-0790-xx, not programmed on TE0790-xxL |
Table 2: Initial delivery state of programmable devices on the module.
Signals, Interfaces and Pins
2x6 Pin Header
The 2x6 pin header (2.54mm grid size, female) J2 have to be connected to the corresponding pin header on the target system. The signal assignment of the pin header on the adapter board depends on the configuration of the System Controller CPLD firmware.
Basic pin assignment:
| Signal | J2 Pin Name | J2 Pin Name | Signal |
|---|---|---|---|
| GND | 1* | GND | |
| User Defined | C | A | User Defined |
| VIO | VDD 3.3V | ||
| User Defined | D | B | User Defined |
| User Defined | F | E | User Defined |
| User Defined | H | G | User Defined / Button (Reset_n) |
Table 3: Pin header J2 signal assignment. *pin 1 on header J2
Top View |
Bottom View flipped |
Figure 3: J2 pin header signal assignment
The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.
Therefore, different signal assignments are made on the pin header J2 depending on the SC CPLD firmware:
Signal assignment on TE0790 CPLD - XMOD Standard:
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| ADBUS0 | TCK (output from adapter) | C | A | up | UART RXD (input to adapter) | BDBUS1 | |
| VIO | - | - | VDD 3.3V | ||||
| ADBUS2 | TDO (input to adapter) | up | D | B | UART TXD (output from adapter) | BDBUS0 | |
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | ||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2
Signal assignment on Standard with RXD-TXD Swapped:
This is the same as the standard configuration except that UART RXD and TXD pins are swapped.
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| ADBUS0 | TCK (output from adapter) | C | A | UART TXD (output from adapter) | BDBUS0 | ||
| VIO | - | - | VDD 3.3V | ||||
| ADBUS2 | TDO (input to adapter) | up | D | B | up | UART RXD (input to adapter) | BDBUS1 |
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | ||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2
Signal assignment on TE0790 CPLD - XMOD DIP40:
On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin. UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| BDBUS1 | UART RXD (input to adapter) | up | C | A | TCK (output from adapter) | ADBUS0 | |
| VIO | - | - | VDD 3.3 V | ||||
| BDBUS0 | UART TXD (output from adapter) | D | B | TMS (output from adapter) | ADBUS3 | ||
| ADBUS1 | TDI (output from adapter) | F | E | up | TDO (input to adapter) | ADBUS2 | |
| not used | H | G | CPLD User LED 'ULED' |
Table 6: Pin header J2 signal assignment with DIPFORTy firmware.
USB Interface
The USB2.0 interface is provided by the FTDI FT2232H chip accessible by the Mini-USB B connector J4. The entire USB protocol is handled on chip and compatible to USB2.0 High Speed (480 MBps) and Full Speed (12 MBps).
On-board Peripherals
FTDI FT2232H IC
The FTDI FT2232H chip provides a variety of industry standard serial or parallel interfaces. On the TE0790 adapter board at current available SC CPLD firmware the functions USB2.0 to JTAG, UART and user GPIO's.
By programing the firmware of the SC CPLD and special EEPROM configurations further further functionalities are available of the FTDI chip which converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.
Configuration EEPROM
The external EEPROM can be used to customize the TE0790 adapter board by setting numerous parameters of the FT2232H IC, enabling different functionalities and configuring serial or parallel interfaces.
The EEPROM is programmable in-circuit over USB using a utility program called FT_PROG available from FTDI’s web site (www.ftdichip.com).
Important notice on TE0790-xx variants:
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.
Signals of the serial or parallel interfaces are by-passed, forwarded and controlled by the System Controller CPLD.
The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2 depends on its configured firmware. CPLD can be set into JTAG chain via S2-1 DIP Switch. Refer to the TE0790 CPLD Firmware for more information about the currently available System Controller CPLD firmware and for download.
DIP-switch
The DIP-switch S2 is to set different modes of powering the on-board peripherals and their I/O supply voltages.
Further functionalities are to secure the EEPROM content and to enable configuring the SC CPLD by JTAG interface:
| S2 | ON | OFF | Default | Description |
|---|---|---|---|---|
| 1 | Normal mode | Module update mode | ON | Update Mode JTAG access to SC CPLD only |
| 2 | Do not use (illegal setting) | Normal mode | OFF | Must be in OFF state always. |
| 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | User I/O Voltage |
| 4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
Table 7: DIP-switch S2 setting description.
The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches S2-3 and S2-4:
| S2-3 | S2-4 | 3.3V (VCC) Pin 5 | VIO Pin 6 | Description |
|---|---|---|---|---|
| OFF | OFF | 3.3V from base | VIO from base | 3.3V (pin 5) and VIO (pin 6) sourced from base |
| OFF | ON | 3.3V from USB* | VIO from base | VIO sourced from base by Pin 6 |
| ON | OFF | 3.3V from base | 3.3V from base | VIO sourced by Pin 6 and drive Pin 5 |
| ON | ON | 3.3V from USB* | 3.3V from USB* | 3.3V (pin 5) and VIO (pin 6) sourced USB |
Table 8: DIP-switch S2 power setting description. *Attention: don't supply voltage from base if pin sourced from USB! For more details see Power supply of the adapter board section.
User Push Button
The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.
On-board LEDs
The on-board LEDs indicates system status data transmission activities:
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | 3.3V | 3.3V power status LED |
| D2 | Red | FTDI IC, 'RXLED' | UART receive data activity |
| D3 | Red | FTDI IC, 'TXLED' | UART transmit data activity |
| D4 | Red | SC CPLD, 'ULED' | user LED, on standard SC CPLD firmware assigned to pins E and G, in DIPFORTy to G |
Table 9: On-board LEDs.
Power and Power-On Sequence
Power supply of the adapter board
The XMOD can be powered via USB or with 3.3V on J2 pins, depending on DIP-switch settings. Max. ~100mA for external components are available on J2 3.3V Pin, if the power supply via USB is used.
Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 determines the configuration of the on-board voltages:
Figure 4: TE0790 on-board voltages configuration
Power Rails
Power Rail Name | Pin Header J2 | Mini USB B J4 | Direction | Notes |
|---|---|---|---|---|
| 3.3V | pin 5 | - | both possible | on-board peripherals' VCC and core voltages |
| VIO | pin 6 | - | both possible | Pin header J2 interface signals and SC CPLD VCCIO |
| VBUS | - | pin 1 | input | USB bus power, nominal voltage 5 V ± 5% |
Table 10: power rails.
Variants Currently In Production
Module Variant | Xilinx Vivado/SDK Support | Xilinx devices with 3rd Party Tools | Any other MPSSE based JTAG Tools |
|---|---|---|---|
| TE0790-02 | Yes | Yes | Yes |
| TE0790-02L | No | Yes | Yes |
Table 11: Module variants.
Variants with TE-0790-xxL do not include the ID String in EEPROM for direct support from Xilinx Vivado.
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
3.3V | -0.3 | 4 | V | FTDI FT2232H data sheet |
| VIO | -0.5 | 3.75 | V | Lattice MachX02 Family data sheet |
| VBUS | 4.75 | 5.25 | V | USB2.0 Specification |
| Voltage on pins A - H | -0.5 | 3.75 | V | Lattice MachX02 Family data sheet |
| Storage temperature | -40 | 100 | °C | LED SML-P11 data sheet |
Table 12: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
3.3V | 2.375 | 3.6 | V | Lattice MachX02 Family data sheet |
| VIO | 1.14 | 3.6 | V | Lattice MachX02 Family data sheet |
| VBUS | 4.75 | 5.25 | V | USB2.0 Specification |
| Voltage on pins A - H | 1.14 | 3.6 | V | Lattice MachX02 Family data sheet |
| Operating temperature | -40 | 85 | °C | FTDI FT2232H data sheet |
Table 13: Module recommended operating conditions.
Operating Temperature Range
Industrial grade: -40°C to +85°C.
The TE0790 USB2.0 adapter board is capable to be operated at industrial grade temperature range.
Physical Dimensions
Module size: 24,65mm × 20,02mm. Please download the assembly diagram for exact numbers.
Mating height with standard pin headers: 9.5 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 7 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters and mil.
Figure 5: Module physical dimensions drawing.
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 | prototypes | - | - |
| - | 02 | current available revision | - | TE0790-02 |
Table 14: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Figure 6: Module hardware revision number.
Document Change History
Date | Revision | Contributors | Description |
|---|---|---|---|
| Ali Naseri |
| ||
2017-10-26 | v.27 | John Hartfiel |
|
| 2017-10-19 | v.26 | Ali Naseri |
|
Table 15: Document change history.
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