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On-board QSPI flash memory (U5) on the TE0726 is provided by Cypress Semiconductor Serial NOR Flash Memory S25FL127SABMFV10 with 128 Mbit (16 MByte) storage capacity connected to the PS MIO bank (MIO1 ... MIO6) of the Zynq SoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA Zynq PS MIO-bank allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
DDR3L SDRAM
The TE0726 SoM is equipped with one DDR3L-1600 SDRAM module with 1 GByte memory density. The SDRAM module is connected to the Zynq SoC's PS DDR controller with 16-bit data bus-width.
Clocking
Signal Name | Clock IC | Default Frequency | Destination IC | Pin | Notes |
|---|---|---|---|---|---|
| PS_CLK | U14 | 33.333333 MHz | U1 | C7 | Zynq SoC system reference clock. |
| OSCI | U7 | 12.000000 MHz | U3 | 3 | FT2232H oscillator input. |
| CLK24M | U2 | 24 MHz (see also REFSEL0 .. 2) | U18 | 26 | Reference input/output clock, see datasheet. |
| CLK25M | U13 | 25.000000 MHz | U2 | 61 | External 25 MHz crystal input. |
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