Page History
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| RGPIO Pin from FPGA | Value |
|---|---|
| 0 | PLL_RSTn |
| 1 | PERSTn |
| 2 | FMC_FAN_EN |
| 7 | LED_N |
| 8 | LED_P |
| 9 | HDLED_N |
| 10 | HDLED_P |
| 12-23 | unused |
| 24-27 | reserved |
| 28-31 | Interface detection |
LED
| LED2 D6 Green (near FAN1 connector on PCB) | ||
|---|---|---|
| Mode | Blink Sequence | Comment |
| PWROK | ******** | ATX Power failed or PCB is powered off |
| PG_LPD | *****ooo | Module Low Power Domain failed |
| PG_FPD | ****oooo | Module Full Power Domain failed |
| PG_PL | ***ooooo | Module PL Power Domain failed |
| POK_1V8 or POK_FMC | **oooooo | Carrier 1V8 or FMC VADJ Power Domain failed |
| PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0' | *ooooooo | Module DDR, PL GT, PS GT or PLL Power Domain failed |
| OFF | All Ready | |
| LED3 D7 Red (near FAN1 connector on PCB) | ||
|---|---|---|
| Mode | Blink Sequence | Comment |
| Error | ******** | ATX Power failed or PCB is powered off |
| JTAG | *****ooo | Module Low Power Domain failed |
| PG_FPD | ****oooo | Module Full Power Domain failed |
| PG_PL | ***ooooo | Module PL Power Domain failed |
| POK_1V8 or POK_FMC | **oooooo | Carrier 1V8 or FMC VADJ Power Domain failed |
| PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0' | *ooooooo | Module DDR, PL GT, PS GT or PLL Power Domain failed |
| OFF | All Ready | |
This Chapter need redesign for CPLD REV06
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Overview
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