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PSON signal will be enabled/disabled after delay, when Power Button is pressed. Power Button is debounced.

StagePower Enable SignalEnable Power domainNote
1PSON ATX PSON (12V from ATX power supply)Signal will be enabled/disabled after delay, when Power Button is pressed.Power Button is debounced.
2PWROK(ATX Power)

5V_EN (5V)

Note 1: If S4-4 is on, 5V is always on.  S4-4 must be on, if TEBF0808 is used with external 12V instead of ATX Power.
Note 2: CPLD Pullup is used for PWROK to works without external 12V only.

2PWROKMOD_EN (Module 3.3V), EN_LPD, EN_FPD, EN_PLModule B2B connector Main Power and enables
3PG_FPDEN_DDR, EN_PLL_PWR, EN_PSGTRModule periphery power
3PG_PLEN_GT_R, EN_GT_LModule periphery power
4PG_FPD and PG_PLPER_EN(Periphery 3.3V), EN_1V8(Periphery 1.8V), PCI_SFP_EN (PCIe and SFP)Carrier periphery power
4PWROK and PG_FPD and PG_PL and PSON and Master CPLD statusFMC_EN (FMC VADJ)FMC VADJ
5PWROK and PG_FPD and PG_PL and PSON and POK_FMC(VADJ)FMC_PG_C2MFMC supply power status to FMC connector

Note: Power Status is visible on LEDs, see LED section

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RGPIO Pin from FPGAValue
0PLL_RSTn
1PERSTn
2FMC_FAN_EN
7LED_N
8LED_P
9HDLED_N
10HDLED_P
12-23unused
24-27reserved
28-31Interface detection

 

LED

LED2 D6 Green (near FAN1 connector on PCB)
 Mode
 Power FlagsBlink SequenceComment
PWROK********ATX Power failed or PCB is powered off
PG_LPD*****oooModule Low Power Domain failed
PG_FPD****ooooModule Full Power Domain failed
PG_PL***oooooModule PL Power Domain failed
POK_1V8 or  POK_FMC**ooooooCarrier 1V8 or FMC VADJ Power Domain failed
PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0'*oooooooModule DDR, PL GT, PS GT or PLL Power Domain failed

OFFAll Ready


LED3 D7 Red (near FAN1 connector on PCB)
 Mode
Bode ModeBlink SequenceComment
Error********ATX Power failed or PCB is powered off
JTAG*****oooModule Low Power Domain failed
PG_FPD
PJTAG0****ooooModule Full Power Domain failed
PG_PL
eMMC***oooooModule PL Power Domain failed
POK_1V8 or  POK_FMC
SPI Boot**ooooooCarrier 1V8 or FMC VADJ Power Domain failed
PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0'*oooooooModule DDR, PL GT, PS GT or PLL Power Domain failedOFFAll Ready

This Chapter need redesign for CPLD REV06

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SD Boot*oooooooModule DDR, PL GT, PS GT or PLL Power Domain failed

ONReset is on


XMOD LED  Red (XMOD1 on J12 with green dot)
StatusBlink SequenceComment
PS_INIT_B********

Indicates the PS is initialized after a power-on reset (POR).

PS_ERROR_OUT*****ooo

The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU.

DONEON or OFF

Indicates the PL configuration is completed (LED is OFF).


LED_P/N (BLUE Power LED  on enclosure)
Status/ UserBlink SequenceComment
Power******** (slow blink)

Indicate board is powered off.

RGPIO controlled User Defined

RGPIO 14 and 15, if RGPIO is active.

MIO40User Defined

MIO40, if RGPIO is deactivated


HDLED_P/N (Red HD LED  on enclosure)
Status/ UserBlink SequenceComment
PS_INIT_B********

Indicates the PS is initialized after a power-on reset (POR).

PS_ERROR_OUT*****ooo

The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU.

ERR_STAT****oooo

The PS_ERROR_STATUS indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status.

RGPIO controlledUser Defined

RGPIO 16 and 17, if RGPIO is active

SC0User DefinedSC0 (PL IO), if RGPIO is deactivated

Blink Frequency:

Blink SequenceComment

*slow_blink: ~0,7 Hz

*mode_blink:

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********~5,8 Hz

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*****ooo~0,7 Hz, duty cycle 5/8

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****oooo~0,7 Hz, duty cycle 4/8

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***ooooo~0,7 Hz, duty cycle 3/8

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**oooooo~0,7 Hz, duty cycle 2/8

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*ooooooo~0,7 Hz, duty cycle 1/8

Appx. A: Change History

Revision Changes

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