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Table of Contents

Table of Contents

Overview


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The Carrier Board provides soldering-pads for VG96 connectors as place-holders to get access to the PL-IO-banks and other functional units of the mounted SoM.

Key Features

  • Barrel jack for 5V power supply
  • 2x RJ45 10/100-BaseT Ethernet MagJack with 2 integrated LEDs
  • 1x RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs.
  • 2x Configuration EEPROM's, connected to SoM's I²C interface
  • XMOD compatible header to connect the TE0790 USB2.0 adapter board
  • JTAG and UART interface over XMOD header
  • MicroSD Card socket, can be used to boot system
  • Micro-USB socket connected to Zynq module (device, host or OTG modesUSB2.0 socket (Option: USB Type A or Micro USB2.0 B)
  • 4-bit DIP switch for SoM configuration (SoM's JTAG access and Bootmode)
  • VG96 connector soldering-pads J8 for access to SoM's PL-IO-bank-pins, usable as LVDS-pairs
  • VG96 connector soldering-pads J9 for access to further interfaces and IO's of the SoM
  • 1 x user LED (red) routed to SoM IO-pin
  • 1 x user push-button routed to SoM (Reset function at standard configuration)
  • Pin headers to set PL-IO-bank's VCCIO
  • Pin header for supplying SoM's VBAT voltage
  • Footprint for optional USB2.0 Type A socket
  • with jumper

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image RemovedImage Added

Figure 1: TEB0729-02 03 block diagram.

Main Components

 

Figure 2: TEB0729-02 03 main components (picture shows PCB REV02).

  1. 5V barrel jack, J12
  2. RJ-45 Gigabit Ethernet MegJack, J3
  3. RJ-45 10/100-BaseT Ethernet MegJack, J4
  4. RJ-45 10/100-BaseT Ethernet MegJack, J5
  5. VG96 connector placeholder, J9
  6. XMOD (TE0790) header, JB3
  7. 2-pin header for VBAT-IN supply-voltage, J2
  8. 2x6 pin header for setting VCCIO_33, J6
  9. 2x6 pin header for setting VCCIO_13, J7
  10. MicroSD Card socket, J1
  11. Red LED, D1
  12. Push Button, S1
  13. Micro USB2.0 B Receptacle (optional USB2.0 Type A socket)
  14. VG96 connector placeholder, J8
  15. B2B Connector, JB1
  16. B2B Connector, JB2
  17. 4-bit DIP-switch, S2

Initial Delivery State

Storage device name

Content

Notes

Configuration EEPROM, U1

Empty

Not programmed
Configuration EEPROM, U2EmptyNot programmed

Table 1: Initial delivery state of programmable devices on the module.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM due to its hermaphroditic structure. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as  as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:

VG96
B2B Connector
Designator
InterfacesCount of IO
'sCount of LVDS-pairsAvailable VCCIO
's
Interfaces
Notes
JB1
72481.8V, 2.5V
User IO24 single ended-
48 single ended or 24 differential
-
-
JB2
645VCCIO_13, VCCIO_33
3.3V

User IO

54 single ended-
10 single ended or 5 differential-
I²C2-
SD IO7-
UART2-
USB2.06-
I²C,
SD IO,
UART,
USB2.0,
2x 10/100-BaseT Ethernet
,
12-
GbE MDI and SGMII
,
JTAG
14
The 5 LVDS
-
pairs on connector JB2 have
the prefix 'DISP' in the schematic net names.

The I²C, SD IO and the UART interface pins are connected
to MIO-pins of the mounted Zynq-SoM, so this pins can also be
used for user and general purposes.

JTAG4-

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

VG96 Connector

The TEB0729 Carrier Board has soldering pads provides as place-holders to mount VG96 connectors J8 and J9 to get access the PL-IO-bank's pins and further interfaces of the Zynq SoM. With mounted VG96 connectors, SoM's IO's are available to the user, a large quantity of these I/O's are also usable as  LVDS-pairs.

On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip device and of its on-module peripherals:

Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:

VG96 ConnectorControl Signals and InterfacesCount of IO's
Count of LVDS-pairsInterfaces
SoM Control Signals
Notes
J8
72
User IO24 single ended
48
-
-
48 single ended or 24 differential-
J9
645

I²C
GbE SGMII

User IO

54 single ended-
10 single ended or 5 differential-
'NRST_IN'
,
(pin J9-A29
Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 1)'NRST_OUT', pin J9-B30Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 1)
), 'RST_STATUS' (pin J9-B30)2

These pins are dedicated to the specific Reset-functionality of the TE0729 SoM.

'BOARD_STAT'
,
(pin J9-B32
Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E).
)1-
'BOOT_MODE1'
,
(pin J9-C31
Bootmode pin 1, use in conjunction with Bootmode pin 2.
), 'BOOT_MODE2'
,
(pin J9-C32)
Bootmode pin 2, use in conjunction with Bootmode pin 1.
2Binary bootmode code of SoM, also connected to DIP S2
I²C2I²C1 interface of module
GbE SGMII4SGMII interface of on-module GbE PHY

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

1) Use TE0729 SC CPLD firmware 'SC729_rev02org.jed' for correct functionality with HW modification.

JTAG Interface

JTAG Interface

JTAG access to the mounted JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip device on the mounted SoM can be programed via USB2.0 interface.

JTAG Signal

B2B Connector Pin

XMOD Header JB3Note
TCKJB2-119JB3-4-
TDIJB2-115JB3-10-
TDOJB2-117JB3-8-
TMSJB2-113JB3-12-
JTAGSELJB2-111-Select SoM's JTAG programming mode on DIP-switch S2-1.

Table 4: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JB3Note
USART0_RXJB2-94JB3-7UART receive line
USART0_TXJB2-96JB3-3UART transmit line

Table 5: UART interface signals.

I²C Interface

Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:

I²C Signal Schematic NameB2BConnected toNote
I2C0_SDAJB2-90EEPROMs U1, U2I²C data line
I2C0_SCLJB2-92EEPROMs U1, U2I²C clock line
I2C1_SDAJB2-93J9-A30I²C data line
I2C1_SCLJB2-95J9-A31I²C clock line

Table 6: I²C interface signals.

SD IO Interface

The SD IO interface of the SoM's Zynq chip device (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip device can be booted from an inserted MicroSD Card:

SD IO Signal Schematic NameB2BConnected toNote
ESD_DAT0JB2-108J1-7SD IO data
ESD_DAT1JB2-110J1-8SD IO data
ESD_DAT2JB2-100J1-1SD IO data
ESD_DAT3JB2-102J1-2SD IO data
ESD_CLKJB2-106J1-5SD IO clock
ESD_CMDJB2-104J1-3SD IO command
MIO0JB2-87J1-9Card Detect signal

Table 7: SD IO interface signals.

USB2.0 Interface

The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-03B, USB2.0 Type A socket is fitted on board-revision TEB0729-03A.

The differential data signals of the USB2.0 socket J11 are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The Micro USB USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with an USB load a power distribution switch U3 to provide the USB USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. The Carrier Board provides the footprints J10 to equip the board with an USB2.0 Type A socket as an option (OTG mode OTG mode is not available with USB2.0 Type A socket).

Following table gives an overview of the USB2.0 interface signals:

USB2.0 Signal Schematic NameB2BConnected toNote
OTG-D_N

JB2-103

J11-2, (J10-2)USB2.0 data
OTG-D_PJB2-101J11-3, (J10-3)USB2.0 data
OTG-IDJB2-109J11-4Ground this pin for A-Device (host),  left floating this pin for B-Device (peripheral).
VBUS_V_ENJB2-97U3, pin 4Enable USB-VBUS.
USB-VBUSJB2-107J11-1, (J10-1)USB supply voltage in Host mode.
USB_OCJB2-48, J9-B29U3, pin 5USB-VBUS over current signal: current-limit threshold exceeded by the connected USB device in USB Host mode.

Table 8: USB2.0 interface signals and connections.

Gigabit Ethernet Interface

The TEB0729 Carrier Board is fitted with one RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:

GbE PHY Signal Schematic NameB2BConnected toNotes
PHY_MDI0_P

JB2-84

J3-2 -
PHY_MDI0_NJB2-82J3-3-
PHY_MDI1_PJB2-78J3-4-
PHY_MDI1_NJB2-76J3-5-
PHY_MDI2_PJB2-72J3-6-
PHY_MDI2_NJB2-70J3-7-
PHY_MDI3_PJB2-66J3-8-
PHY_MDI3_NJB2-64J3-9-
PHY_LED0JB2-59Green MegJack J3 LED-
PHY_LED1JB2-57Green MegJack J3 LED-

Table 9: GbE interface signals and connections.


For the same GbE transceiver PHY on the mounted SoM, on the Carrier Board is also a SGMII (Serial Gigabit Media Independent Interface) available. The SGMII pins are available on VG96 connector J9:

GbE PHY Signal Schematic NameB2BConnected toNotes
SIN_P

JB2-52

J9-A16 -
SIN_NJB2-54J9-A17-
SOUT_PJB2-58J9-A19-
SOUT_NJB2-60J9-A20-

Table 10: GbE SGMII signals and connections.

10/100-BaseT Ethernet Interface

The TEB0729 Carrier Board is also fitted with two additional RJ-45 MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2

10/100-BaseT PHY Signal Schematic NameB2BConnected toNotes
ETH1_RX_P

JB2-26

J4-3 -
ETH1_RX_NJB2-28J4-6-
ETH1_TX_PJB2-20J4-1-
ETH1_TX_NJB2-22J4-2-
ETH1_
CTREFJB2-30J4-4, J4-5Centre Tap Reference pointETH1_
LED0JB2-34Yellow MegJack J4 LED-
ETH1_LED1JB2-32Green MegJack J4 LED-




ETH2_RX_PJB2-8J5-3-
ETH2_RX_NJB2-10J5-6-
ETH2_TX_PJB2-2J5-1-
ETH2_TX_NJB2-4J5-2
-ETH2_CTREFJB2-18
J5-4, J5
-
5
Centre Tap Reference point
ETH2_LED0JB2-16Yellow MegJack J5 LED-
ETH2_LED1JB2-14Green MegJack J5 LED-

Table 11: 10/100-BaseT Ethernet interfaces signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via header JB3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB interface. The TE0790 board provides also an UART interface to the Zynq SoM which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted. The adapter-board offers also two GPIO's, one with an indication LED (pin JB3-9 (E)) and another one with a low-active push button (pin JB3-11 (G)).

Following table describes the signals and interfaces of the XMOD header JB3:

JB3 pinSignal Schematic Net NameB2BNote
C (pin 4)TCKJB2-119
 
-
D (pin 8)TDOJB2-117
 
-
F (pin 10)TDIJB2-115
 
-
H (pin 12)TMSJB2-113
 
-
A (pin 3)USART0_TXJB2-96
 
-
B (pin 7)USART0_RXJB2-94
 
-
E (pin 9)BOARD_STATJB2-112also connected to VG96 connector pin J9-B32
G (pin 11) 2)NRST_INJB2-89

also connected to VG96 connector pin J9-A29

Table 12: XMOD header signals and connections.  2) Pin connected to push button S1 on XMOD FTDI JTAG Adapter

When using XMOD FTDI JTAG Adapter TE0790, set the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

  • S2-1: ON
  • S2-2: OFF
  • S2-3: OFF
  • S2-4: ON

...

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4ON

Table 13: XMOD adapter board DIP-switch positions for voltage configuration.


Note

Use Xilinx compatible TE0790 adapter board (designation TE0790-xx with out 'L') to program the Zynq device.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

On-board Peripherals

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Configuration EEPROM

The TEB0729 Carrier Board is equipped with two Configuration EEPROMs U1 and U2 from Microchip.

...

The Configuration EEPROMs are connected to the I²C0 interface of the Zynq's MIO-bank via B2B connector JB2.

4-bit DIP-switch

Table below describes DIP-switch S2 settings for configuration of the mounted SoM:

DIP-switches S2Signal Schematic Net NameFunctionNote
S2-1JTAGSEL

Select Zynq

chip

device or SC CPLD programming of mounted SoM

on DIP-switch S2-1.OFF:  Zynq chip programming.

:

OFF:  Zynq device in JTAG chain
ON:   

SC

CPLD

programming

in JTAG chain

Depends also on SoM's SC CPLD firmware configuration.
Refer also to the TE0729 SC CPLD documentation for detailed information about JTAG update
S2-2BOOT_MODE1Select first bit of
Zynq chips bootmode
boot mode codeRefer to TE0729 TRM and SC CPLD documentation for detailed information about boot modes
.
S2-3BOOT_MODE2Select second bit
of Zynq chips bootmode
boot mode code
-
S2-4xxnot used

Table 1314: DIP-Switch S2 SoM configuration settings.

VCCIO Setting Jumper


Boot ModeS2-2S2-3
JTAGONON
SDOFFOFF
QSPIONOFF

Table 15Boot Modes configuration via DIP-switch S2 with default TE0729 CPLD Firmware

VCCIO Selection Jumper

The Carrier Board VCCIO for the PL IO-banks of the The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

Following table describes how to configure the VCCIO of the SoM's banks with jumpers:

VCCIO
vs.
voltage levels
Voltage LevelsVCCIO_13VCCIO_33Note
1.8VJ7:pins 1-2J6: pins 1-2-
2.5VJ7: pins 3-4J6: pins 3-4-
3.3VJ7: pins 5-6J6: pins 5-6-

Table 1416: VCCIO jumper settings.

RTC Buffer Voltage Supply Header

The buffer voltage of the SoM's RTC can be supplied through the header J2. Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.

Push Button

The Carrier Board's push button S1 is connected to the 'NRST_IN' signal of , the mounted SoM. The function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

On-board LEDs

LED ColorConnected toDescription and Notes
D1Red'MIO9', pin JB2- 88user LED

Table 1517: On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends the Carrier Board depends mainly on the mounted SoM's FPGA design running on the FPGAZynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
5VINTBD*

Table 1618: Typical power consumption.

...

Warning
To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:


Image Added

Figure 3: Board Figure : Module power distribution diagram.

 

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Power Rails

Power Rails

The voltage direction of the power rails is directed at on-board connectors' view:

Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

VIN33

Out

1, 2, 3, 4, 5, 6

3.3V module supply voltage
VCCIO_13Out101, 102PL IO-bank VCCIO
VCCIO_33Out29, 30PL IO-bank VCCIO
3.3VIn65, 66voltage output from module
JB2

1.8V

In

49

voltage output from module
2.5VIn13voltage output from module
USB-VBUSOut107USB Host supply voltage
VBAT_INOut118RTC buffer voltage

Table 19: Power pin description of B2B Module Connector.


Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J6VCCIO_33In2, 4, 6-
1.8VOut5-
2.5VOut3-
3.3VOut1-
J7

VCCIO_13

In2, 4, 6-
1.8VOut5-
2.5VOUt3-
3.3VOut1-

Table 20: Power Pin description of VCCIO selection jumper pin header.


Main Power Jack and Pins
Module Connector (B2B)
DesignatorVCC / VCCIODirectionPinsNotes
JB1
J12
VIN33
5VIN
Out
In

Pin 1, 2, 3, 4, 5, 6

3.3V module supply voltageVCCIO_13OutPin 101, 102PL IO-bank VCCIOVCCIO_33OutPin 29, 30PL IO-bank VCCIO3.3VInPin 65, 66voltage output from moduleJB2

1.8V

In

Pin 49

voltage output from module2.5VInPin 13voltage output from moduleUSB-VBUSOutPin 107USB Host supply voltageVBAT_INOutPin 118RTC buffer voltage

Table 17: Power pin description of B2B Module Connector.

1

-
J95VINIn / OutA1, A2also usable as '5VIN' power supply to the Carrier Board as alternative to J12
J2VBAT_INIn1Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.


Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J10 / J11USB-VBUSIn / Out1Direction depends on USB2.0 mode
J1VIN33Out4MikroSD Card socket VDD

Table 22: Power pin description of peripheral connector.


XMOD
Jumper /
Header DesignatorVCC / VCCIODirectionPinsNotes
J6VCCIO_33OutPin 2, 4, 6-1.8VIn5-2.5VIn3-3.3VIn1-J7

VCCIO_13

OutPin 2, 4, 6-1.8VIn5-2.5VIn3-3.3VIn1-

Table 18: Power Pin description of VCCIO selection jumper pin header.

...

-

...

JB33.3V-5not connected
VIOOut6connected to VIN33

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.

Order
number

REF NumberSamtec NumberTypeMated HeightData sheetComment
-REF-189019-02BTE-060-01-L-D-A-K-TRModule connector5 mmhttp://suddendocs.samtec.com/catalog_english/bte.pdfStandard connector
used on module
26663REF-189019-01BSE-060-01-L-D-A-TRBaseboard connector5 mmhttp://suddendocs.samtec.com/catalog_english/bse.pdfStandard connector
used on board

Table 24: B2B Connectors.


Connector SpecificationsValue
Insulator materialLiquid crystal polymer
Stacking height5 mm
Contact materialPhosphor-bronze
PlatingAu or Sn over 50 μ" (1.27 μm) Ni
Current rating2 A per pin (1 pin powered per row)
Operating temperature range-55 °C to +125 °C
Voltage rating225 VAC with 5 mm stack height
Max cycles100
RoHS compliantYes

Table 25: B2B Connector specifications.

Variants Currently In Production

 Module Variant

Operating Temperature

USB SocketTemperature Range
TEB0729-03-A-40°C to +125°CUSB2.0 Type A socket fittedIndustrial
TEB0729-03-B-40°C to +125°CMicro USB2.0 B socket fittedIndustrial

Table 26: Board

Table 19: Main Power jack and pins description.

...

Table 20: Power pin description of peripheral connector.

...

Table 21: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

...

Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

...

Operating Temperature

...

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN

5VIN supply voltage

 -0.3
 
 7

V

-
MP5010A, EN6347QI data sheet

Storage temperature

 -65

 
150

°C

-

Table 27: Module absolute maximum ratings.

...

...

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN
5VIN supply voltage
   
 4.755.25 VUSB2.0 specification concerning 'VBUS' voltage
 
Operating temperature -40
 
125
 
°C
 
-

Table : Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

...

28: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TEB0729 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall systemModule operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Board size: 107.70 mm × 100 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... 8 mm.

  • PCB thickness: ca. 1.65mm. mm.

  • Highest part on PCB: approx. ... mmon the PCB is the Ethernet RJ-45 jack, which has an approximately 17 mm overall height. Please download the step model for exact numbers.

All dimensions are given in millimeters.


       

Figure 4: Board physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link-

01

Prototypes

  

Notes

PCNDocumentation Link
-

01

  • First Production Release
 -TEB0729-01
-02
  • Second Production Release
  • HW-Modification since 22.08.2017
  • Refer to Changes list in Schematic

    for further details in changes to REV01

-TEB0729-02
-03
  • Rework Reset-Signals by Pin-Swap
  • Refer to Changes list in Schematic for
    further details in changes to REV02
-TEB0729-03

Table 29Table : Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Image AddedPut picture of actual PCB showing model and hardware revision number here...

Figure 5: Module hardware revision number.

Document Change History

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Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->


Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseri
  • update TRM to board revision 03

2017-10-27

v.14
Ali Naseri
  • initial document to board revision 02

Table 30: Document change history.

Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices