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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/4x5+Module+Integration+Guide |
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Table of Content |
Power and Signal Pin Assignment
How to Use This Guide
- This guide is split into two tables:
- The PCBs have fixed and variable user supplied I/O voltage pins. Variable power supply pins are colored in four groups (VCCIOA, VCCIOB, VCCIOC and VCCIOD).
- Find your module model on the Module Power Connection Table and check the power supply of the different FPGA banks.
- If the power supply is variable(colored), go to the Carrier Board Power Connection Table and see how it's connected on your carrier board. Often the power source can be selected by jumper, resistor or variable used from other connector pin of the carrier board. So use the schematic name or the component designator from the table to search for the available options in the PCB schematics or TRM.
- Additional Master Pinout Viewer/XDC-Generator is available on Trenz Electronic Download - Pinout
Module Power Connection Table
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title | Module B2B FPGA-Banks and Voltages |
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Group | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
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Module Model | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | | | TE0710 | B15 | 48 | HR | VCCIOA | - | - | - | - | - | - | - | - | B34 | 50 | HR | VCCIOD | B16 | 6 | HR | 3.3V | B14 | 8 | HR | 3.3V | 2x 100Mbit ETH | | | | | | TE0711 | B15 | 48 | HR | VCCIOA | B34 | 36 | HR | VCCIOB | B14 | 18 | HR | 3.3V | B35 | 50 | HR | VCCIOD | B16 | 6 | HR | 1.8V | B14 | 8 | HR | 3.3V | B34 | 8 | HR | VCCIOB | | USB | TE0712 | B16 | 48 | HR | VCCIOA | B13 | 20 | HR | VCCIOB | B14 | 18 | HR | 3.3V | B15 | 50 | HR | VCCIOD | B13 | 6 | HR | VCCIOB | B14 | 8 | HR | 3.3V | 1x 100Mbit ETH / B13 | 4 | HR | VCCIOB | | B14 | TE0713 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TE0715-xx-15 | B13 | 48 | HR | VCCIOA | B34 | 16 | HR | VCCIOC | B34 | 18 | HR | VCCIOC | B35 | 40 | HR | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH | | | | SGMII | USB | TE0715-xx-30 | B13 | 48 | HR | VCCIOA | B34 | 16 | HP | VCCIOC | B34 | 18 | HP | VCCIOC | B35 | 40 | HP | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH | | | | SGMII | USB | TE0720 | B35 | 48 | HR | VCCIOA | B34 | 36 | HR | VCCIOB | B33 | 18 | HR | VCCIOC | B13 | 50 | HR | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH | | | | SGMII | USB | TE0820* | B25 B26 | 48 | HD | VCCIOA | | | | | | | | | B64 | 50 | HR | VCCIOD | | 6 | MIO | 1.8V | | 8 | MIO | 3.3V | 1x Gbit ETH | | | | | | TE0741 | B13 | 48 | HR | VCCIOA | B16 | 16 | HR | VCCIOB | B15 | 18 | HR | VCCIOC | B12 | 50 | HR | VCCIOD | GTX | 1 Lane | | | B14 | 8 | HR | 3.3V | GTX | 2 Lanes | | | GTX | | TE0742* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TE0841 | B64 | 48 | HR | VCCIOA | B66 | 16 | HP | VCCIOB | B68 | 18 | HP | VCCIOC | B67 | 50 | HP | VCCIOD | GTH | 1 Lane | | | B65 | 8 | HR | 3.3V | GTH | 2 Lanes | | | GTH | | TE0842* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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title | Module basic power and group pin assignment, recommended to verify with Schematics |
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Carrier Board Power Connection Table
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title | Power Pin Connection on different Carrierboards |
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IO Voltage | B2B Connector | Carrier Boards |
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Name | Direction* | JB1 | JB2 | TE0701 | TE0703 Rev 01 - Rev 04 | TE0703 Rev 05 | TE0705 | TE0706 | TEBA0841 REV02 | | | Pin | Pin | Schematic Name | Value,Option,Comp. | Schematic Name | Value,Option,Comp. | Schematic Name | Value,Option,Comp. | Schematic Name | Value,Option,Comp. | Schematic Name | Value,Option,Comp. | Schematic Name | Value,Option,Comp. | PWR_1 | out | 2,4,6 | 1,3,5,7 | 5V0 | 5V | 3.3V | 3.3V | 3.3V | 3.3V | 5V0 | 5V | 3.3V | 3.3V | 3.3V | use ext. 3.3V power supply | VCCIOA | out | 10,12 | | VIOTB | FMC_VADJ 2V5 3.3VOUT | VCCIO35 | R23→M3.3VOUT J1B-B1 | VCCIOA | J5→M3.3VOUT, M1.8VOUT R23→M3.3VOUT J1-B1 | VIOTB | FMC_VADJ 2V5 3.3VOUT | VCCIO35 | R20->M3.3VOUT/J6B-B32 | VCCIOA | J26→ M1.8VOUT, 2.5V, 3.3V_OUT J20-6,J20-45 | VCCIOD | out | | 8,10 | VIOTB | FMC_VADJ 2V5 3.3VOUT | VCCIO13 | R26→M3.3VOUT J2B-B1 | VCCIOD | J10→M3.3VOUT, M1.8VOUT R26→M3.3VOUT J2B-B1 | VIOTB | FMC_VADJ 2V5 3.3VOUT | VCCIO13 | R22->M3.3VOUT/J6B-B1 | VCCIOD | J27→ M1.8VOUT, 2.5V, 3.3V_OUT J17-6,J17-45 | PWR_2 | out | 14,16 | | 3V3IN | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V | 3V3IN | 3.3V | 3.3V | 3.3V | | | VCCIOB | out | | 2,4 | no name / VIOTA
| FMC_VADJ 2V5 3.3VOUT | VCCIO34 | J5→M3.3VOUT J1B-B32 | VCCIOB | J8→M3.3VOUT,M1.8VOUT J2B-B32 | VIOTB | FMC_VADJ 2V5 3.3VOUT | 1.8V | 1.8V | VCCIOB | NC | VCCIOC | out | | 6 | no name / VIOTA
| FMC_VADJ 2V5 3.3VOUT | VCCIO33 | R25→M3.3VOUT J2B-B32 | VCCIOC | J9→M3.3VOUT, M1.8VOUT R25→M3.3VOUT J2B-B32 | VIOTB | FMC_VADJ 2V5 3.3VOUT | VCCIO33 | R21->M3.3VOUT | VCCIOC | NC | PWR_M1 | in | | 9,11 | 3.3VOUT | 3.3V | 3.3VOUT | 3.3V | M3.3VOUT | 3.3V | 3.3VOUT | 3.3V | M3.3VOUT | 3.3V | 3.3V_OUT | 3.3V | PWR_M2 | in | 40 | | VIOB | 1.8V | M1.8VOUT | 1.8V | M1.8VOUT | 1.8V | VIOB | 1.8V | M1.8VOUT | 1.8V | M1.8VOUT | 1.8V | PWR_M3 | in | | 20 | NC | | NC | | NC | | NC | | NC | | | NC | PWR_VBAT | out | 80 | | VBAT | B1 | VBAT | J7 | VBAT | J7 | NC | | VBAT | J9 | VBAT | NC | | in | | 92 | VCCJTAG | | VCCJTAG | | VCCJTAG | | VCCJTAG | | VCCJTAG | | VCCJTAG | NC |
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title | Carrierboard basic power and group pin assignment (Top View), recommended to verify with Schematics |
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Carrier Board Checklist
Schematic Checklist
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1 | Are B2B pin numbers on the connectors mirrored compared to the module pin numbers? | As B2B connectors are "unisex" type the do mirror pin numbers when connecting. That is pin1 connects to pin2, and pin2 to pin1, etc. |
2 | Are B2B connectors named JB1, JB2, JB3? | This is not a hard requirement, but it helps to use the same identifiers. |
3 | Are all GND pins connected to a common ground net? | |
4 | Are all VIN pins connected together? | |
5 | Is JB2 pin 92 pin used as VREF for the JTAG interface? | for future compatibility only, currently all modules have 3.3V JTAG |
6 | Are external circuits/buffers connecting to MIO bank 1 pins powered from JB1 pin 40? | JB1 pins 18, 20, 22, 24, 26, 28 use voltage at pin 40 as VCCIO. Currently it is 1.8V for all released modules. |
PCB Checklist
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1 | Are mounting holes placed properly? | Four Mounting holes should always be used. They are required for mounting screws and for module extraction. The mounting holes will also help in dissipating some heat from the module to the carried board PCB. Four holes with a 3.2mm diameter should be placed exactly at the corners of a 34mm by 44mm rectangle. |
2 | Are B2B headers properly placed? | B2B headers must be placed and aligned very precisely or the module will not align correctly (in the worst case module insertion could destroy the connectors or the PCB). The B2B headers should be locked on the PCB, and it is recommended that the position and placement be checked against placement dimensions before submitting the PCB files. |
3 | Are B2B headers rotated properly? | As B2B header pin numbers differ from module to the carrier (swap of odd and even numbers), it is recommended that that the rotation is checked in the PCB design. |
4 | Height clearance below module | Components can be placed below the module but height clearance rules must be obeyed. |
5 | Power dissipation of components below module | It is not recommended to place any components with high power dissipation below the module, as there will be almost no airflow below the module. |
Visual Check of Module placement
It is highly recommended to use the Base board Template designs as a starting point for new PCB designs. If that is not possible, then adding linear dimensions in the design helps to check that all connectors and mounting holes are properly placed.
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