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Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TEBB0714+TRMTEM0001 for the current online version of this manual and other available documentation.

The Trenz Electronic TEBB0714 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi Gigabit Transceiver units of the TE0714 module. Although this base-board is dedicated to the TE0714 module, it is also compatible with other Trenz Electronic 4 x 3 cm SoMs. See page "4 x 3 cm carriers" to get information about the SoMs supported by the TEBB0714 Carrier Board.

This base-board provides also solder pads as place-holders for pin headers as option to get access to the PL I/O-bank pins and further of the mounted TE 4 x 3 SoM.

Key Features

• SFP+ connector (Enhanced small form-factor pluggable), support data transmission rates up to 10 Gbit/s
• 4 Hirose Ultra small SMT coaxial connectors, support data transmission rates up to 6 Gbit/s
• TE 4 x 3 cm SoM programmable by XMOD header (JX1)
• 2 x user LEDs routed to I/O-pins of the SoM
• Solder pads J17 and J20 for optional pin headers for access to SoM's PL I/O-bank pins, usable as LVDS pairs
• Solder pads J3 and J4 for optional pin headers for access to further interfaces and I/O's of the SoM

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TEBB0714-01 Block Diagram.

Main Components

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Figure 2: TEBB0714-01 Carrier Board.

1. 6-pin header J26 for selecting PL-bank I/O voltage
2. 6-pin header J27 for selecting XMOD/JTAG VCCIO
3. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
4. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
5. XMOD header, JX1
6. Ultra small SMT coaxial connector, J5
7. Ultra small SMT coaxial connector, J6
8. Ultra small SMT coaxial connector, J7
9. Ultra small SMT coaxial connector, J8
10. User LED D1 (green)
11. User LED D2 (red)
12. LED D3 (red) indicating FPGA's 'Programming DONE'-signal
13. SFP+ Connector, J1
14. 10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
15. 16-pin header solder pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
16. 50-pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
17. 50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

Initial Delivery State

Board is shipped in following configuration:

• VCCIO voltage selection jumpers are all set to 1.8 V.
• Pin headers (not soldered to the board, but included in the package as separate component)

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TEBB0714 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

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Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Pin Header

The TEBB0714 Carrier Board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

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User I/O

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Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

SFP+ Connector

The TEBB0714 Carrier Board is equipped with one SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JM1, the control-lines are connected to B2B connector JM2.

Following table describes the pin-assignment of the SFP+ connector in detail:

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Table 3: SFP+ connector pin-assignment.

Ultra Small SMT Coaxial Connectors

4 HIROSE Ultra Small Surface Mount Coaxial Connectors (up to 6 Gbit/s transmission rate) are present on the Carrier Board available for access to one MGT lane of the SoM. The connectors have the manufacturer designation 'U.FL-R-SMT-1', mating hight: 2.4 mm.

Each conductor of the RX and TX differential pair is routed to one coaxial connector:

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Table 4: Pin-assignment of the coaxial connectors.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

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JTAG Signal

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B2B Connector Pin

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Table 5: JTAG interface signals.

XMOD FTDI JTAG-Adapter Header JX1

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, so in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

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When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board's and module's 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

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OFF

Table 7: XMOD adapter board DIP-switch positions for voltage configuration.

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TEM0001 is a low cost small-sized FPGA module integrating a Microsemi SmartFusion2 FPGA SoC and 8 MByte Flash memory for configuration and operation.

Key Features

• Microsemi SmartFusion2 SoC FPGA

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• 25 MHz system clock and 32.768 KHz auxiliary clock
• JTAG and UART over Micro USB connector
• 1x 3-pin header for Live Probes
• 1x PMOD header providing 8 I/O

• 2x 14-pin headers (2,54 mm pitch) providing 23 I/O

• 9 user LEDs

• 1 user push button
• 3.3V single power supply with on-board voltage regulators
• Size 61.5 x 25 mm
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TEM0001-01 block diagram

Main Components

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Figure 2: TEM0001-01 FPGA module

1. Microsemi SmartFusion2 FPGA SoC, U5
2. 8 Mbyte SDRAM 166MHz, U2
3. Micro USB2 B socket (receptacle), J9
4. Switch button (reset), S1
5. Switch button (user), S2
6. Red LED (user), D10
7. Green LED (indicating supply voltage), D1
8. 8x red LEDs (user), D2 - D9
9. FTDI USB2 to JTAG/UART interface, U3
10. 8 Mbyte QSPI Flash memory, U1
11. 32.768 KHz auxiliary crystal, Y1
12. 25 MHz main crystal, Y2
13. 1x14 pin header (2.54mm pitch), J2
14. 1x6 pin header (2.54mm pitch), J4
15. 3-pin header (2.54mm pitch), J3
16. 1x14 pin header (2.54mm pitch), J1
17. 2x6 Pmod connector, J6

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

There is are no bootmode selection Microchip SmartFusion2 SoC boots always from internal configuration flash, optionally software code for the Cortex-M or soft CPU can be placed to eNVM.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table 3: General overview of FPGA I/O banks

JTAG Interface

JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is implemented with FTDI FT2232H USB2 to JTAG/UART bridge IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG header

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

Table 5: QSPI interface signals

Note: On-board SPI Flash is connected to regular FPGA I/O pins, access to it is only possible when using custom SPI flash IP core or via MSS subsystem SPI when it is connected via fabric to those pins. There is no automatic boot from this flash.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2.

FTDI FT2232H IC

FTDI FT2232H Channel A works as JTAG interface compatible to Libero tools. Channel B is connected to FPGA pins with direct access to MSS UART peripheral.

The configuration of FTDI FT2232H is pre-programmed to the EEPROM U9 to make it work as FlashPro5 interface for Libero tools.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Table 6: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

Table 8: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEM0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

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Figure 3: Power Distribution Diagram

Power Consumption

Table 9: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Technical Specifications

Absolute Maximum Ratings

Table 10: Absolute maximum ratings

Recommended Operating Conditions

Table 11: Recommended operating conditions

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

• Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.65mm

• Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

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Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History

Table 12: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Figure 5: Module hardware revision number

Document Change History

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V_CFG Value

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Table 8: Setting of reference I/O-voltage XMOD header.

JTAG/UART Header J3

As alternative to the XMOD header JX1, on the Carrier Board pin header J3 is present, which has a XMOD header-compatible pin-assignment, but also 4 additional pins as differential pairs to supply the mounted SoM with an external MGT reference clock signal and as differential analog signal input:

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Table 9: JTAG/UART header J3 signals and connections.

UART Interface

UART interface is available on B2B connector JM2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

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Table 10: UART interface signals.

QSPI Interface

The QSPI interface (if available) of the mounted SoM is routed to the pin header J17. The reference I/O-voltage of the module have to be noticed when using this interface.

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Table 11: QSPI interface signals.

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

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Figure 12: On-board LEDs

VCCIO Selection Jumper

On the TEBB0714 Carrier Board the PL-bank I/O voltage (schematic name 'VCCIO34') can be selected by the jumper J26.

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VCCIO34 Value

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Table 13: Base-board PL-bank I/O voltage setting.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 14: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

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JX1-5, JX1-6,

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Table 15: Connector pins capable for external 3.3V power supply

Power Distribution Dependencies

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM1-83 and JM2-54, meaning that all on-module voltages have become stable and module is properly powered up.

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Figure 3: Board power distribution diagram.

Power Rails

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3.3V

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97, 99

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1.8V

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18

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Table 16: Power pin description of B2B module connector.

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3.3V

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5, 46

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3.3V

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5, 46

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Table 17: Power Pin description of on-board connector.

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Table 18: Power Pin description of VCCIO selection jumper pin header.

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Table 19: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

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Technical Specifications

Absolute Maximum Ratings

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Vin supply voltage

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3.135

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V

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Storage Temperature

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°C

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Table 20: Board absolute maximum ratings.

Recommended Operating Conditions

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Table 21: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TEBA0841 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

• Board size:  PCB 46mm ×  75mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the SFP+ connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• Mating height of the module with standard connectors: 8mm

• PCB thickness: ca. 1.65mm

• Highest part on the PCB is the SFP+ connector, which has an approximately 11.3 mm overall hight. Please download the step model for exact numbers.

 The dimensions are given in mm and mil (milli inch).

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Figure 4: Board physical dimensions drawing.

Revision History

Hardware Revision History

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Notes

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01

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• First Production Release

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Table 22: Module hardware revision history.

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Figure 5: Board hardware revision number.

Document Change History

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Date

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Revision

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Contributors

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Description

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• First TRM release

Table 23: Document change history.Table 13: Document change history

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