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Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TE0706+TRMTEM0001 for the current online version of this manual and other available documentation.

The Trenz Electronic TE0706 Carrier Board provides functionalities for testing, evaluation and development purposes of company's 4 x 5 cm SoMs. The Carrier Board is equipped with various components and connectors for different configuration setups and needs. The interfaces of the SoM's functional units and PL I/O-banks are connected via board-to-board connectors to the Carrier Board's components and connectors for easy user access.

See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.

Key Features

• 3 x Samtec LSHM Series Board to Board Connectors
• VG96 connector (mounting holes and solder pads, J6) and 50-pin IDC male connector socket (J5) for access to PL I/O-bank pins
• Micro SD card socket
• SDIO port expander with voltage-level translation
• USB2.0 type A connector, optionally Micro USB 2.0 connector
• 1 x user-push button S2, by default configured as system reset button
• 1 x RJ45 GbE MagJack J3, connected via MDI to B2B connector JB1
• 1 x Marvell Alaska 88E1512 GbE PHY, providing Ethernet interface in conjunction with RJ45 GbE MagJack J2
• 5V power supply barrel jack
• 4 A High-Efficiency Power SoC DC-DC Step-Down Converter (Enpirion EN6347) for 3.3V power supply
• XMOD JTAG- / UART-header JX1
• DIP-switch S1 to set Som's System Controller CPLD control signals
• 3 x VCCIO selection jumper J10, J11 and J12 to set SoM's PL I/O-bank voltages

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TE0706-02 block diagram.

Main Components

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Figure 2: TE0706-02 Carrier Board

1. 5V power connector jack, J1
2. Reset switch, S2
3. USB2.0 type A receptacle, J7
4. Micro SD card socket with Card Detect, J4
5. 50 pin IDC male connector, J5
6. 1000Base-T Gigabit RJ45 Ethernet MagJack, J3
7. 1000Base-T Gigabit RJ45 Ethernet MagJack, J2
8. XMOD JTAG- / UART-header, JX1
9. User DIP-switch, S1
10. VCCIO selection jumper block, J10 - J12
11. External connector (VG96) placeholder, J6
12. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
13. Samtec Razor Beam™ LSHM-150 B2B connector, JB2
14. Samtec Razor Beam™ LSHM-130 B2B connector, JB3

Initial Delivery State

Board is shipped in following configuration:

• VCCIO voltage selection jumpers are all set to 1.8 V.
• S2 switch configured as reset button.
• One VG96 connector (not soldered to the board, but included in the package as separate component)

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TE0706 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1, JB2 and JB3:

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Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Connector

The TE0706 Carrier Board has and a 50-pin IDC male connector J5 and soldering pads as place-holder to mount a VG96 connectors J6 to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these connectors, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the connectors J5 and J6:

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User I/O

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Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

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JTAG Signal

...

B2B Connector Pin

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Table 3: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

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Table 4: UART interface signals.

I²C Interface

One of the SoM's I²C interface is routed to the on-board connector J5 and is available to the user for general purposes:

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Table 5: I²C interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the on-board Texas Instruments TXS02612 SDIO port expander U4. This IC provides a necessary VDD/VCCIO translation between the MicroSD Card socket J4 (3.3V) and the SoM's Zynq device MIO-bank (1.8V):

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Table 6: SD IO interface signals.

USB2.0 Interface

TE0706-02 board has one physical USB2.0 type A socket J7, the differential data signals of the USB2.0 socket are routed to the B2B connector JB3, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

There is also the option to equip the board with a Micro USB 2.0 type B (receptacle) socket (J8) to the board as alternative fitting option. With this fitting option (Micro USB2.0 type B), the USB2.0 interface can also be used for Device mode, OTG and Host Modes.

For USB2.0 Host mode, the Carrier Board is additionally equipped with a power distribution switch U5 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

Following table gives an overview of the USB2.0 interface signals:

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JB2-48

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Table 7: USB2.0 interface signals and connections.

Gigabit Ethernet Interface

The TE0706 Carrier Board is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U6), which provides in conjunction with the Gigabit Ethernet MagJack J2 a 1000Base-T Ethernet (GbE) interface. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied by on-board 25MHz oscillator (U7).

The GbE MegJack J2 has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the GbE PHY.

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JB3-47,

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Reduced Gigabit Media Independent Interface.

12 pins.

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Serial Gigabit Media Independent Interface.

Not connected.

...

Media Dependent Interface.

Connected to Gigabit Ethernet MagJack J2.

Table 8: GbE interface signals and connections.

RJ45 Gigabit Ethernet MagJack J3

The TE0706-02 carrier board is also equipped with a second Gigabit-Ethernet MagJack J3, which is connected via MDI to the B2B connector JB1.

There is usually a corresponding Gigabit Ethernet PHY on 4 x 5 SoMs (e.g. TE0715 or TE0720), which can be used in conjunction with the baseboard MagJack J3.

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JB1-3

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Table 9: RJ45 GbE MagJack signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

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Table 10: XMOD header signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the mounted SoM's 'VCCJTAG' (pin JB2-92). Set the DIP-switch with the setting:

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On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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4-bit DIP-switch

Table below describes DIP-switch S1 settings for configuration of the mounted SoM:

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Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware).

...

Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware).

Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM.

TEM0001 is a low cost small-sized FPGA module integrating a Microsemi SmartFusion2 FPGA SoC and 8 MByte Flash memory for configuration and operation.

Key Features

• Microsemi SmartFusion2 SoC FPGA

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• 25 MHz system clock and 32.768 KHz auxiliary clock
• JTAG and UART over Micro USB connector
• 1x 3-pin header for Live Probes
• 1x PMOD header providing 8 I/O

• 2x 14-pin headers (2,54 mm pitch) providing 23 I/O

• 9 user LEDs

• 1 user push button
• 3.3V single power supply with on-board voltage regulators
• Size 61.5 x 25 mm
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TEM0001-01 block diagram

Main Components

Image AddedImage Added

Figure 2: TEM0001-01 FPGA module

1. Microsemi SmartFusion2 FPGA SoC, U5
2. 8 Mbyte SDRAM 166MHz, U2
3. Micro USB2 B socket (receptacle), J9
4. Switch button (reset), S1
5. Switch button (user), S2
6. Red LED (user), D10
7. Green LED (indicating supply voltage), D1
8. 8x red LEDs (user), D2 - D9
9. FTDI USB2 to JTAG/UART interface, U3
10. 8 Mbyte QSPI Flash memory, U1
11. 32.768 KHz auxiliary crystal, Y1
12. 25 MHz main crystal, Y2
13. 1x14 pin header (2.54mm pitch), J2
14. 1x6 pin header (2.54mm pitch), J4
15. 3-pin header (2.54mm pitch), J3
16. 1x14 pin header (2.54mm pitch), J1
17. 2x6 Pmod connector, J6

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

There is are no bootmode selection Microchip SmartFusion2 SoC boots always from internal configuration flash, optionally software code for the Cortex-M or soft CPU can be placed to eNVM.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table 3: General overview of FPGA I/O banks

JTAG Interface

JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is implemented with FTDI FT2232H USB2 to JTAG/UART bridge IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG header

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

Table 5: QSPI interface signals

Note: On-board SPI Flash is connected to regular FPGA I/O pins, access to it is only possible when using custom SPI flash IP core or via MSS subsystem SPI when it is connected via fabric to those pins. There is no automatic boot from this flash.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2.

FTDI FT2232H IC

FTDI FT2232H Channel A works as JTAG interface compatible to Libero tools. Channel B is connected to FPGA pins with direct access to MSS UART peripheral.

The configuration of FTDI FT2232H is pre-programmed to the EEPROM U9 to make it work as FlashPro5 interface for Libero tools.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Table 6: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

Table 8: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEM0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

Image Added

Figure 3: Power Distribution Diagram

Power Consumption

Table 9: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Technical Specifications

Absolute Maximum Ratings

Table 10: Absolute maximum ratings

Recommended Operating Conditions

Table 11: Recommended operating conditions

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

• Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.65mm

• Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

Image Added      Image Added

Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History

Table 12: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Figure 5: Module hardware revision number

Document Change History

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Figure 3: User DIP-switch S1

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The Carrier Board VCCIO for the PL I/O-banks of the mounted SoM are selectable by the jumpers J10, J11 and J12.

Following table describes how to configure the VCCIO of the SoM's PL I/O-banks with jumpers:

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Only one supply-source is allowed to configure the base-board supply-voltages, either by jumper, by 0-Ohm-resistor or by connector J6. If a supply-voltage is configured by 0-Ohm-resistor or connector J6, then the corresponding configuration-jumper has to be removed. There aren't 0-Ohm-resistors and supply-voltages by connector J6 allowed if the corresponding base-board supply-voltage is configured by jumper. Vice versa jumpers and 0-Ohm-resistors have to be removed if supplying corresponding base-board supply-voltage by connector J6.

Note: If supplying base-board supply-voltages by connector J6, the module's internal 3.3V voltage-level on pins 9 and 11 of B2B-connector JB2 has to be reached stable state.

RTC Buffer Voltage Supply Header

The buffer voltage of the SoM's RTC can be supplied through the header J9 (VBAT-pin). Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.

Push Button

The Carrier Board's push button S2 is connected to the 'RESIN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 14: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Distribution Dependencies

The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:

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Figure 5: Board power distribution diagram.

Power Rails

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3.3V

...

2, 4, 6, 14, 16

...

1.8V

...

2, 4

...

Table 15: Power pin description of B2B module connector.

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3.3V

...

6, 45

...

VCCIOA

...

B32

...

Table 16: Power Pin description of on-board connector.

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VCCIOB

...

Table 17: Power Pin description of VCCIO selection jumper pin header.

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-

...

Table 18: Main Power jack and pins description.

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Table 19: Power pin description of peripheral connector.

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Table 20: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

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Variants Currently In Production

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Operating Temperature

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Table 21: Board variants.

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

5VIN supply voltage

...

V

...

Storage temperature

...

 -55

...

°C

...

Table 22: Module absolute maximum ratings.

Recommended Operating Conditions

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Table 23: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TE0706 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

• Board size:  PCB 100mm ×  64.5mm. Notice that the USB type A socket on the left and the Ethernet RJ-45 jacks on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106mm. Please download the assembly diagram for exact numbers.

• Mating height of the module with standard connectors: 8mm

• PCB thickness: 1.65mm

• Highest parts on the PCB are USB type A socket and the Ethernet RJ-45 jacks, approximately 15mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

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Figure 6: Board physical dimensions drawing.

Revision History

Hardware Revision History

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Notes

...

01

...

• Prototypes

...

• First Production Release
• Refer to Changes list in Schematic

  for further details in changes to REV01

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Table 24: Module hardware revision history.

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Figure 7: Board hardware revision number.

Document Change History

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Table 25: Document change history.Table 13: Document change history

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