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Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TEBA0841+TRMTEM0001 for the current online version of this manual and other available documentation.

The Trenz Electronic TEBA0841 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi-gigabit transceiver units of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 base-board.

Key Features

• SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
• Micro USB2.0 Type B Connector (J10)
• Trenz 4x5 module Socket (3 x Samtec LSHM series connectors)
• 4 x 5 SoM programmable by XMOD JTAG/UART header (JX1)
• 2 x user LEDs routed to I/O-pins of the SoM
• Soldering-pads J17 and J20 for optional pin headers for access to SoM's I/O-bank-pins, usable as LVDS-pairs
• Soldering-pads J3 and J4 for optional pin headers for access to further interfaces and I/O's of the SoM

TEM0001 is a low cost small-sized FPGA module integrating a Microsemi SmartFusion2 FPGA SoC and 8 MByte Flash memory for configuration and operation.

Key Features

• Microsemi SmartFusion2 SoC FPGA

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• 25 MHz system clock and 32.768 KHz auxiliary clock
• JTAG and UART over Micro USB connector
• 1x 3-pin header for Live Probes
• 1x PMOD header providing 8 I/O

• 2x 14-pin headers (2,54 mm pitch) providing 23 I/O

• 9 user LEDs

• 1 user push button
• 3.3V single power supply with on-board voltage regulators
• Size 61.5 x 25 mm
  
  

Additional assembly options are available for cost or Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TEBA0841 TEM0001-01 Block Diagram.block diagram

Main Components

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Figure 2: TE0706-02 Carrier Board.

1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
2. Samtec Razor Beam™ LSHM-150 B2B connector, JB3
3. Samtec Razor Beam™ LSHM-130 B2B connector, JB2
4. 6-pin header J26, for selecting PL I/O-bank voltage
5. 6-pin header J27, for selecting PL I/O-bank voltage
6. Micro USB2.0 Type B Connector J12 (Device or OTG mode)
7. JTAG/UART header, JX1 ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
8. User LED D1 (green)
9. User LED D2 (red)
10. SFP+ Connector, J1
11. 50-pin header soldering-pads J17, for access to PL I/O-bank pins (LVDS-pairs possible)
12. 50-pin header soldering-pads J20, for access to PL I/O-bank pins (LVDS-pairs possible)
13. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
14. 10-pin header soldering-pads J4, for access to SoM's SDIO-port, if available

Initial Delivery State

Board is shipped in following configuration:

• VCCIO voltage selection jumpers are all set to 1.8 V.
• Pin headers (not soldered to the board, but included in the package as separate component)

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TEBA0841 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

...

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Pin Header

The TEBA0841 Carrier Board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

...

User I/O

...

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

SFP+ Connector

On the TEBA0841 carrier board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JB2, the control-lines are connected to B2B connector JB1 and are assigned to MIO-bank pins of the mounted SoM.

The pin-assignment of the SFP connector is in detail as fellows:

...

Table 1: SFP+ connector pin-assignment.

¹⁾ Important: For proper operation, a wire patch to GND is done at recently delivered boards. Connect to GND, if not done. See PCB drawing below:

Image Removed

Figure 3: PCB wire patch for SFP+ connector.

Looped-backed MGT-Lanes on B2B Connector JB1 and JB2

The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification. 

The MGT lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:

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JB2-8 (MGT_TX0_N)

JB2-10 (MGT_TX0_P)

...

JB2-7 (MGT_RX0_N)

JB2-9 (MGT_RX0_P)

...

JB2-7 to JB2-8

JB2-9 to JB2-10

...

JB2-14 (MGT_TX1_N)

JB2-16 (MGT_TX1_P)

...

JB2-13 (MGT_RX1_N)

JB2-15 (MGT_RX1_P)

...

JB2-13 to JB2-14

JB2-15 to JB2-16

...

JB2-20 (MGT_TX2_N)

JB2-22 (MGT_TX2_P)

...

JB2-19 (MGT_RX2_N)

JB2-21 (MGT_RX2_P)

...

JB2-19 to JB2-20

JB2-21 to JB2-22

...

JB1-3 (MGT_TX7_P)

JB1-5 (MGT_TX7_N)

...

JB1-9 (MGT_RX7_P)

JB1-11 (MGT_RX7_N)

...

JB1-3 to JB1-9

JB1-5 to JB1-11

...

JB1-15 (MGT_TX6_P)

JB1-17 (MGT_TX6_N)

...

JB1-21 (MGT_RX6_P)

JB1-23 (MGT_RX6_N)

...

JB1-15 to JB1-21

JB1-17 to JB1-23

 TEM0001-01 FPGA module

1. Microsemi SmartFusion2 FPGA SoC, U5
2. 8 Mbyte SDRAM 166MHz, U2
3. Micro USB2 B socket (receptacle), J9
4. Switch button (reset), S1
5. Switch button (user), S2
6. Red LED (user), D10
7. Green LED (indicating supply voltage), D1
8. 8x red LEDs (user), D2 - D9
9. FTDI USB2 to JTAG/UART interface, U3
10. 8 Mbyte QSPI Flash memory, U1
11. 32.768 KHz auxiliary crystal, Y1
12. 25 MHz main crystal, Y2
13. 1x14 pin header (2.54mm pitch), J2
14. 1x6 pin header (2.54mm pitch), J4
15. 3-pin header (2.54mm pitch), J3
16. 1x14 pin header (2.54mm pitch), J1
17. 2x6 Pmod connector, J6

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

There is are no bootmode selection Microchip SmartFusion2 SoC boots always from internal configuration flash, optionally software code for the Cortex-M or soft CPU can be placed to eNVM.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table 3: General overview of FPGA I/O banks

JTAG Interface

JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is implemented with FTDI FT2232H USB2 to JTAG/UART bridge IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG header

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

Table 5: QSPI interface signals

Note: On-board SPI Flash is connected to regular FPGA I/O pins, access to it is only possible when using custom SPI flash IP core or via MSS subsystem SPI when it is connected via fabric to those pins. There is no automatic boot from this flash.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2.

FTDI FT2232H IC

FTDI FT2232H Channel A works as JTAG interface compatible to Libero tools. Channel B is connected to FPGA pins with direct access to MSS UART peripheral.

The configuration of FTDI FT2232H is pre-programmed to the EEPROM U9 to make it work as FlashPro5 interface for Libero tools.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Table 6: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

Table 8: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEM0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

Image Added

Figure 3: Power Distribution Diagram

Power Consumption

Table 9: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Technical Specifications

Absolute Maximum Ratings

Table 10: Absolute maximum ratings

Recommended Operating Conditions

Table 11: Recommended operating conditions

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

• Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.65mm

• Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

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Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History

Table 12: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Added

Figure 5: Module hardware revision number

Document Change History

Table 2: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

...

JTAG Signal

...

B2B Connector Pin

...

Table 3: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

...

Table 4: UART interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

...

Table 6: SD IO interface signals.

USB2.0 Interface

TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.

Following table gives an overview of the USB2.0 interface signals:

...

JB2-48

...

Table 7: USB2.0 interface signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1 and pin header J3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal.

So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:

...

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the DIP-switch with the setting:

...

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

...

Figure 3: On-board LEDs

VCCIO Selection Jumper

On the TEBA0841 carrier board different VCCIO configurations can be selected by the jumper J26 and J27.

TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on their B2B connectors, which will be fed with I/O voltage from base-board.

...

Base-board PL-bank I/O Voltages

...

Table 5: Base-board PL-bank I/O voltages VCCIOA and VCCIOD

Following table describes how to configure the base-board supply-voltages by jumpers:

...

Base-board PL-bank I/O Voltages
vs Voltage Levels

...

Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

Table 14: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

...

JX1-5, JX1-6,

...

Table 4: Connector pins capable for external 3.3V power supply

Power Distribution Dependencies

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM2-10 and JM2-12, meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram shows the distribution of the external input voltage of nominal 3.3V to the components:

Image Removed

Figure 5: Board power distribution diagram.

Power Rails

...

3.3V

...

2, 4, 6, 14, 16

...

1.8V

...

2, 4

...

Table 15: Power pin description of B2B module connector.

...

3.3V

...

6, 45

...

VCCIOA

...

B32

...

Table 16: Power Pin description of on-board connector.

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VCCIOB

...

Table 17: Power Pin description of VCCIO selection jumper pin header.

...

-

...

Table 18: Main Power jack and pins description.

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Table 19: Power pin description of peripheral connector.

...

Table 20: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

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Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

5VIN supply voltage

...

V

...

Storage temperature

...

 -55

...

°C

...

Table 22: Module absolute maximum ratings.

Recommended Operating Conditions

...

Table 23: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TE0706 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

• Board size:  PCB 100mm ×  64.5mm. Notice that the USB type A socket on the left and the Ethernet RJ-45 jacks on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106mm. Please download the assembly diagram for exact numbers.

• Mating height of the module with standard connectors: 8mm

• PCB thickness: 1.65mm

• Highest parts on the PCB are USB type A socket and the Ethernet RJ-45 jacks, approximately 15mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

Figure 6: Board physical dimensions drawing.

Revision History

Hardware Revision History

...

Notes

...

01

...

• Prototypes

...

• First Production Release
• Refer to Changes list in Schematic

  for further details in changes to REV01

...

Table 24: Module hardware revision history.

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Figure 7: Board hardware revision number.

Document Change History

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Table 25: Document change history.Table 13: Document change history

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