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Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1, JB2 and JB3:

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

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Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the connectors J5 and J6:

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

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JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

Table 3: JTAG interface signals.

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UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

Table 4: UART interface signals.

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One of the SoM's I²C interface is routed to the on-board connector J5 and is available to the user for general purposes:

Table 5: I²C interface signals.

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The SD IO interface of the mounted SoM is routed to the on-board Texas Instruments TXS02612 SDIO port expander U4. This IC provides a necessary VDD/VCCIO translation between the MicroSD Card socket J4 (3.3V) and the SoM's Zynq device MIO-bank (1.8V):

Table 6: SD IO interface signals.

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Following table gives an overview of the USB2.0 interface signals:

Table 7: USB2.0 interface signals and connections.

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The GbE MegJack J2 has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the GbE PHY.

Table 8: GbE interface signals and connections.

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There is usually a corresponding Gigabit Ethernet PHY on 4 x 5 SoMs (e.g. TE0715 or TE0720), which can be used in conjunction with the baseboard MagJack J3.

Table 9: RJ45 GbE MagJack signals and connections.

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Following table describes the signals and interfaces of the XMOD header JX1:

Table 10: XMOD header signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the mounted SoM's 'VCCJTAG' (pin JB2-92). Set the DIP-switch with the setting:

Table 11: XMOD adapter board DIP-switch positions for voltage configuration.

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Table below describes DIP-switch S1 settings for configuration of the mounted SoM:

Table 12: DIP-switch S1 SoM configuration settings.

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Following table describes how to configure the VCCIO of the SoM's PL I/O-banks with jumpers:

Table 13: VCCIO jumper settings.

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 14: Typical power consumption.

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The voltage direction of the power rails is from board and on-board connectors' view:

Table 15: Power pin description of B2B module connector.

Table 16: Power Pin description of on-board connector.

Table 17: Power Pin description of VCCIO selection jumper pin header.

Table 18: Main Power jack and pins description.

Table 19: Power pin description of peripheral connector.

Table 20: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

Variants Currently In Production

Table 21: Board variants.

Technical Specifications

Absolute Maximum Ratings

Table 22: Module absolute maximum ratings.

Recommended Operating Conditions

Table 23: Module recommended operating conditions.

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Hardware Revision History

Table 24: Module hardware revision history.

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Table 25: Document change history.

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