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  • Power Management
  • Reset Management
  • LED Control
  • FAN Control
  • I2C MUX

Firmware Revision and supported PCB Revision

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Name / opt. VHD NameDirectionPinDescription
200MHZCLK_ENout30 
BUTTONin77Reset Button
CPLD_JTAG_TCK 91not accessible as IO
CPLD_JTAG_TDI 94not accessible as IO
CPLD_JTAG_TDO 95not accessible as IO
CPLD_JTAG_TMS 90not accessible as IO
DDR3_SCL  inout43/ currently_not_usedI2C connected to FPGA
DDR3_SDA  inout42/ currently_not_usedI2C connected to FPGA
DONEin18FPGA Done
EN_1V8out58Power Enable
EN_3V3FMCout60Power Enable
EN_FMC_VADJout51Power Enable
F1PWMout98FAN
F1SENSEin99FAN / currently_not_used
FEX_DIR 19/ currently_not_used
FEX0 out12PERST from PCIe slot
FEX1 15/ currently_not_used
FEX10 4/ currently_not_used
FEX11 in10User LED
FEX2 13/ currently_not_used
FEX3 9/ currently_not_used
FEX4 3/ currently_not_used
FEX5 7/ currently_not_used
FEX6 24/ currently_not_used
FEX7 17/ currently_not_used
FEX8 21/ currently_not_used
FEX9 25/ currently_not_used
FMC_PG_C2M 69/ currently_not_used
FMC_PG_M2C 68/ currently_not_used
FMC_PRSNT_M2C_L 70/ currently_not_used
FMC_SCL 49/ currently_not_usedI2C connected to FPGA
FMC_SDA 48/ currently_not_usedI2C connected to FPGA
FMC_TCK 27/ currently_not_used
FMC_TDI 31/ currently_not_used
FMC_TDO 32/ currently_not_used
FMC_TMS 28/ currently_not_used
FMC_TRST 36/ currently_not_used
FPGA_IIC_OE 14I2C FPGA
FPGA_IIC_SCL 1I2C FPGA
FPGA_IIC_SDA 16I2C FPGA
LED1out76Status LED D1 (green)
LTM_1V_IO0 86Power Good
LTM_1V_IO1 88Power Good
LTM_1V5_4V_IO0 85Power Good
LTM_1V5_4V_IO1 83Power Good
LTM_1V5_RUN 74/ currently_not_used
LTM_4V_RUN 75/ currently_not_used
LTM_SCL 67/ currently_not_usedI2C connected to FPGA
LTM_SDA 66/ currently_not_usedI2C connected to FPGA
LTM1_ALERT 65/ currently_not_used
LTM2_ALERT 64/ currently_not_used
PCIE_RSTBin37PERST from PCIe card edge connector
PG_1V8in59Power Good
PG_3V3in61Power Good
PG_FMC_VADJin52Power Good
PLL_SCL inout2I2C SI5338
PLL_SDA inout8I2C SI5338
PROGRAM_Bout20FPGA PROG_B
VID0_FMC_VADJout53FMC EN5365QI power selection pin
VID1_FMC_VADJout54FMC EN5365QI power selection pin
VID2_FMC_VADJout57FMC EN5365QI power selection pin

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200MHz CLK is enabled after power up.

I2C

Connect SI5338, LTM and FMC, SODIMM I2C and internal FAN Control to FPGA I2C Bus.

Si5338 configuration is not implemented.

FAN1

I2C Baseaddress: 0x74 (changeable with Firmware update). I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 20 MHz supported.

Write Access:

Register AddressNameDescription
0FAN CTRLEnable FAN1 (Bit7)
1FAN1 PWMFAN1 PWM (0%-100%, Default 80%)


Read Access:

Register AddressNameDescription
0FAN CTRLFAN Control register
1FAN1 RPSFAN1 Revolutions per second

Button

Button is debounced and controls PROG_B signal from FPGA.

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  • BUGFIX: PCIe Reset
  • USER LED accessible
  • I2C for SI5338, LTM, FMC, SODIMM
  • Add FAN Control over I2C

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.


REV02REV01

Page info
modified-user
modified-user

  • REV02
working in process
  • finished
2017-08-06v.4REV01REV01John Hartfiel
  • REV01 finished
2017-05-29

v.1

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Page info
created-user
created-user

  • Initial release
 All  

Page info
modified-users
modified-users

 

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