Page properties |
---|
|
Template Revision 3.1 Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board" - Change List 3.0 to 3.1
- Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
- Change List 2.9 to 3.0
- add fix table of content
- add table size as macro
- removed page initial creator
|
Page properties |
---|
|
Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
Scroll Title |
---|
anchor | Figure_xyz |
---|
title | Text |
---|
|
Scroll Ignore |
---|
Create DrawIO object here: Attention if you copy from other page, use |
Scroll Only |
---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Example | Comment |
---|
1 | 2 |
...
Date | Version | Changes | Author |
---|
2023-06-13 | 3.1.16 | - Design flow:
- added alternative programming files in Petalinux
- added chapter FSBL Patch in Software Design - Petalinux
| ma | 2023-06-01 | 3.1.15 | - removed u-boot.dtb from Design flow
| ma | 2023-06-01 | 3.1.14 | - expandable lists for revision history and supported hardware
| wh | 2023-05-25 | 3.1.13 | - updated according to Vivado 2022.2
| ma | 2023-02-08 | 3.1.12 | - removed content of
- Special FSBL for QSPI programming
| ma | 2022-08-24 | 3.1.11 | - Modification from link "available short link"
| ma | 2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1.9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
|
|
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
|
Page properties |
---|
|
Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
|
Overview
Scroll Ignore |
---|
scroll-pdf | true |
---|
scroll-office | true |
---|
scroll-chm | true |
---|
scroll-docbook | true |
---|
scroll-eclipsehelp | true |
---|
scroll-epub | true |
---|
scroll-html | true |
---|
|
|
Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).
Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
---|
|
Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
---|
- Vitis/Vivado 2022.2
- TEBF0808
- Linux
- USB
- ETH
- MAC from EEPROM
- PCIe
- SATA
- SD
- I2C
- RGPIO
- Display Port (DP)
- user LED access
- Modified FSBL for Si5345 programming / petalinux patch
|
Revision History
Page properties |
---|
|
Notes : - add every update file on the download
- add design changes on description
|
Expand |
---|
|
Scroll Title |
---|
anchor | Table_DRH |
---|
title-alignment | center |
---|
title | Design Revision History |
---|
| Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Vivado | Project Built | Authors | Description |
---|
2023-08-17 | 2022.2 | TE0807-StarterKit-vivado_2022.2-build_6_20230817092640.zip TE0807-StarterKit_noprebuilt-vivado_2022.2-build_6_20230817092640.zip | Manuela Strücker | - 2022.2 update
- new assembly variants
| 2022-10-17 | 2021.2.1 | TE0807-StarterKit_noprebuilt-vivado_2021.2-build_18_20221017093227.zip TE0807-StarterKit-vivado_2021.2-build_18_20221017093227.zip | Manuela Strücker | | 2022-09-12 | 2021.2.1 | TE0807-StarterKit_noprebuilt-vivado_2021.2-build_15_20220912085654.zip TE0807-StarterKit-vivado_2021.2-build_15_20220912085654.zip | Manuela Strücker | - update board part file compatible to Vivado 2021.2.1
| 2022-05-19 | 2021.2 | TE0807-StarterKit_noprebuilt-vivado_2021.2-build_14_20220519081728.zip TE0807-StarterKit-vivado_2021.2-build_14_20220519081728.zip | Manuela Strücker | - 2021.2 update
- new assembly variants
- update document style
| 2021-02-08 | 2020.2 | TE0807-StarterKit_noprebuilt-vivado_2020.2-build_1_20210208094502.zip TE0807-StarterKit-vivado_2020.2-build_1_20210208093620.zip | John Hartfiel | - 2020.2 update
- add boot.scr file
- device tree has change
- petalinux fsbl patch (betaversion)
| 2020-10-06 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_15_20201006122416.zip TE0807-StarterKit-vivado_2019.2-build_15_20201006122402.zip | John Hartfiel | | 2020-03-25 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325082944.zip TE0807-StarterKit-vivado_2019.2-build_8_20200325082924.zip | John Hartfiel | | 2020-02-19 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_5_20200219124225.zip TE0807-StarterKit-vivado_2019.2-build_5_20200219124212.zip | John Hartfiel | - add missing linux Boot.bin
- small update for SI configuration (FSBL)
| 2020-01-27 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_4_20200127075822.zip TE0807-StarterKit-vivado_2019.2-build_4_20200127075809.zip | John Hartfiel | - 2019.2 update
- Vitis support
- FSBL SI programming procedure update
- petalinux device tree and u-boot update
| 2019-05-22 | 2018.3 | TE0807-StarterKit-vivado_2018.3-build_06_20190522132448.zip TE0807-StarterKit_noprebuilt-vivado_2018.3-build_06_20190522132504.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
- ES2 prebuilt files are not included
| 2019-02-07 | 2018.2 | TE0807-StarterKit_noprebuilt-vivado_2018.2-build_04_20190207111631.zip TE0807-StarterKit-vivado_2018.2-build_04_20190207111616.zip | John Hartfiel | | 2018-09-04 | 2018.2 | TE0807-StarterKit_noprebuilt-vivado_2018.2-build_03_20180904122245.zip TE0807-StarterKit-vivado_2018.2-build_03_20180904121600.zip | John Hartfiel | - small petalinux changes
- IO renaming
- PL Design changes
- additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-05-24 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip | John Hartfiel | | 2018-02-06 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip | John Hartfiel | | 2018-02-05 | 2017.4 | TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip | John Hartfiel | | 2018-01-18 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip | John Hartfiel | |
|
|
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title-alignment | center |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Issues | Description | Workaround/Solution | To be fixed version |
---|
Xilinx Software | Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request | use corresponding board files for the Vivado versions | -- | MAC from EEPROM | The MAC address stored in the EEPROM is not read out and initialised correctly during start-up. This is caused by two I2C expanders each switched to the same EEPROM with the same address i2cswitch@73 --> i2c@5 --> reg = <0x50> and i2cswitch@77 --> i2c@4 --> reg = <0x50> | Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure. | Solved with update | QSPI Flash | Flash programming is not supported with boot mode QSPI or SD.
| If flash programming fails, configure device for JTAG boot mode and try again or use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
| -- | Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180524 update | USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is necessary: - Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
| Solved with 20180205 update |
|
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title-alignment | center |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Software | Version | Note |
---|
Vitis | 2022.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2022.2 | needed | SI ClockBuilder Pro | --- | optional |
|
Hardware
Page properties |
---|
|
Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Expand |
---|
|
Scroll Title |
---|
anchor | Table_HWM |
---|
title-alignment | center |
---|
title | Hardware Modules |
---|
| Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0807-01-07EV-ES | es2_2gb | REV01 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0807-02-07EV-1E | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-07EV-1EK | 7ev_1e_4gb | REV02 |
|
|
Overview
Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).
Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
---|
|
Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
---|
- Vitis/Vivado 2019.2
- TEBF0808
- Linux
- USB
- ETH
- MAC from EEPROM
- PCIe
- SATA
- SD
- I2C
- RGPIO
- DP
- user LED access
- Modified FSBL for Si5338 programming / petalinux patch
- Special FSBL for QSPI Programming
|
Revision History
Page properties |
---|
|
Notes : - add every update file on the download
- add design changes on description
|
Scroll Title |
---|
anchor | Table_DRH |
---|
title | Design Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Date | Vivado | Project Built | Authors | Description |
---|
2021-02-08 | 2020.2 | TE0807-StarterKit_noprebuilt-vivado_2020.2-build_1_20210208094502.zip TE0807-StarterKit-vivado_2020.2-build_1_20210208093620.zip | John Hartfiel | - 2020.2 update
- add boot.scr file
- device tree has change
- petalinuxx fsbl patch (betaversion)
|
2020-10-06 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_15_20201006122416.zip TE0807-StarterKit-vivado_2019.2-build_15_20201006122402.zip | John Hartfiel | |
2020-03-25 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325082944.zip TE0807-StarterKit-vivado_2019.2-build_8_20200325082924.zip | John Hartfiel | |
2020-02-19 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_5_20200219124225.zip TE0807-StarterKit-vivado_2019.2-build_5_20200219124212.zip | John Hartfiel | - add missing linux Boot.bin
- small update for SI configuration (FSBL)
|
2020-01-27 | 2019.2 | TE0807-StarterKit_noprebuilt-vivado_2019.2-build_4_20200127075822.zip TE0807-StarterKit-vivado_2019.2-build_4_20200127075809.zip | John Hartfiel | - 2019.2 update
- Vitis support
- FSBL SI programming procedure update
- petalinux device tree and u-boot update
|
2019-05-22 | 2018.3 | TE0807-StarterKit-vivado_2018.3-build_06_20190522132448.zip TE0807-StarterKit_noprebuilt-vivado_2018.3-build_06_20190522132504.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
- ES2 prebuilt files are not included
|
2019-02-07 | 2018.2 | TE0807-StarterKit_noprebuilt-vivado_2018.2-build_04_20190207111631.zip TE0807-StarterKit-vivado_2018.2-build_04_20190207111616.zip | John Hartfiel | |
2018-09-04 | 2018.2 | TE0807-StarterKit_noprebuilt-vivado_2018.2-build_03_20180904122245.zip TE0807-StarterKit-vivado_2018.2-build_03_20180904121600.zip | John Hartfiel | - small petalinux changes
- IO renaming
- PL Design changes
- additional notes for FSBL generated with Win SDK
- changed *.bif
|
2018-05-24 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip | John Hartfiel | |
2018-02-06 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip | John Hartfiel | |
2018-02-05 | 2017.4 | TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip | John Hartfiel | |
2018-01-18 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip | John Hartfiel | |
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Issues | Description | Workaround/Solution | To be fixed version |
---|
Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180524 update |
USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is nessecary: - Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
| Solved with 20180205 update |
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Software | Version | Note |
---|
Vitis | 2020.2 | needed, Vivado is included into Vitis installation |
PetaLinux | 2020.2 | needed |
SI ClockBuilder Pro | --- | optional |
Hardware
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title |
---|
anchor | Table_HWM |
---|
title | Hardware Modules |
---|
|
Scroll Table Layout |
---|
|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0807-01-07EV-ES | es2_2gb | REV01 | 2GB | 64MB | NA | NA | Not longer supported by vivado |
TE0807-02-07EV-1E | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-07EV-1EK | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-4BE21-A | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DE21-A | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DI21-C | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | without encryption |
TE0807-02-7DI21-A | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-4AI21-A | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-5AI21-A | 5cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7AI21-A | 7cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DI24-A | 7ev_1i_4gb | REV02 | 4GB | 512MB | NA | NA | NA |
TE0807-02-7DE21-AK | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-4AI21-X | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0807-02-4BE21-AK | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-7DI21-AK | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-5DI21-A | 5ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7NE21-A | 7ev_3e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-03-5DI21-A | 5ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7NE21-A | 7ev_3e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-4AI21-X | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0807-03-4AI21-A | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-4AI21-C | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption |
TE0807-03-4BE21-A | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-5AI21-A | 5cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7AI21-A | 7cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7DE21-A | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7DE21-AK | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | with heat sink | TE0807- |
|
037DI217ev1iREV03 REV02 | 4GB | 128MB | NA | NA | NA | TE0807- |
|
037DI21C 1iREV03 without encryption 037DI24A REV03 512MB NA |
Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Scroll Title |
---|
anchor | Table_HWC |
---|
title | Hardware Carrier |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Carrier Model | Notes |
---|
TEBF0808 | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
Additional HW Requirements:
Scroll Title |
---|
anchor | Table_AHW |
---|
title | Additional Hardware |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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DP Monitor | Optional HW Not all monitors are supported, also Adapter to other Standard can make drouble. Design was testet with DELL U2412M |
USB Keyboard | Optional HW Can be used to get access to console which is show on DP |
USB Stick | Optional HW USB was tested with USB memory stick |
Sata Disk | Optional HW |
PCIe Card | Optional HW |
ETH cable | Optional HW Ethernet works with DHCP, but can be setup also manually |
SD card | with fat32 partiton |
Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
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title | Additional design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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SI5345 | <design name>/misc/Si5345 | SI5345 Project with current PLL Configuration |
init.sh | <design name>/sd/ | Additional Initialization Script for Linux |
Prebuilt
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Notes :
prebuilt filesTemplate Table: Scroll Title |
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title | Prebuilt files |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Source | *.scr | Distro Boot file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Debian SD-Image | *.img | Debian Image for SD-Card |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Source | *.scr | Distro Boot file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image Removed - Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (bl31.elf, uboot.elf, image.ub, boot.src, bl31.elf) with exported XSA
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
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Note: - Programming and Startup procedure
|
For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to QSPI-Boot and insered SD.
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area
SD
- Copy image.ub and Boot.bin on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 70156402
- Connect UART USB (JTAG XMOD)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Control:LEDs: XMOD 2(without green dot) and HD LED are accessible. without encryption | TE0807-02-7DI21-A | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-4AI21-A | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-5AI21-A | 5cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7AI21-A | 7cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7DI24-A | 7ev_1i_4gb | REV02 | 4GB | 512MB | NA | NA | NA | TE0807-02-7DE21-AK | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-4AI21-X | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | U41 replaced with diode | TE0807-02-4BE21-AK | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-7DI21-AK | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-5DI21-A | 5ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7NE21-A | 7ev_3e_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-03-5DI21-A | 5ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7NE21-A | 7ev_3e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-4AI21-X | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode | TE0807-03-4AI21-A | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-4AI21-C | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption | TE0807-03-4BE21-A | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-5AI21-A | 5cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7AI21-A | 7cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-A* | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-AK | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | with heat sink | TE0807-03-7DI21-A | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DI21-C | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption | TE0807-03-7DI24-A | 7ev_1i_4gb | REV03 | 4GB | 512MB | NA | NA | NA | TE0807-03-4BE21-AK | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-S004 | 7ev_1e_me_8gb | REV03 | 8GB | 128MB | NA | NA | CAO | TE0807-03-S005 | 7ev_1i_4gb | REV03 | 4GB | 512MB | NA | NA | CAO | TE0807-03-S008 | 7ev_1i_me_8gb | REV03 | 8GB | 128MB | NA | without PLL | CAO Micron DDR | TE0807-03-S014 | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-AZ | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-S011 | 7ev_1i_me_8gb | REV03 | 8GB | 128MB | NA | without PLL | CAO Micron DDR |
*used as reference |
|
Note: Design contains also Board Part Files for TE0807 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
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Carrier Model | Notes |
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TEBF0808* | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
*used as reference |
Additional HW Requirements:
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title | Additional Hardware |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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Display Port Monitor | Optional HW Not all monitors are supported, also Adapter to other Standard can make trouble. Design was testet with DELL U2412M | USB Keyboard | Optional HW Can be used to get access to console which is show on Display Port | USB Stick | Optional HW USB was tested with USB memory stick | SATA Disk | Optional HW | PCIe Card | Optional HW | ETH cable | Optional HW Ethernet works with DHCP, but can be setup also manually | SD card | with fat32 partition |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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cellHighlighting | true |
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
|
Additional Sources
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anchor | Table_ADS |
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title-alignment | center |
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title | Additional design sources |
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repeatTableHeaders | default |
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style | |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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SI5345 | <project folder>\misc\PLL\Si5345_B | SI5345 Project with current PLL Configuration | init.sh | <project folder>\misc\sd | Additional initialization script for Linux |
|
Prebuilt
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Notes : - prebuilt files
- Template Table:
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title | Prebuilt files |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
---|
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block |
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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|
------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Info |
---|
Using Vivado GUI is the same, except file export to prebuilt folder. |
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis
- Copy PetaLinux build image files to prebuilt folder
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Generate Programming Files
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") |
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|
TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
---|
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Page properties |
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Note: - Programming and Startup procedure
|
For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and DebuggingGet prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info |
---|
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs BOOT.bin on QSPI flash) |
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TE::pr_program_flash -swapp hello_te0807 |
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area
SD-Boot mode
- Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr |
- (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional with TEBF0808) Connect SATA Disc
- (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional with TEBF0808) Connect Network Cable
Power On PCB
Expand |
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1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
Code Block |
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language | bash |
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theme | Midnight |
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# password disabled
petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
You can use Linux shell now.
Code Block |
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language | bash |
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theme | Midnight |
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i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check)
lspci (PCIe check) |
Option Features
- Webserver to get access to ZynqMP
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Control:
- LEDs: XMOD 2(without green dot) and HD LED are accessible.
- CAN_S
Scroll Title |
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anchor | Figure_VHM |
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title-alignment | center |
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title | Vivado Hardware Manager |
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Image Added | Image Added Image Added |
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System Design - Vivado
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Block Design
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design |
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Image Added |
PS Interfaces
Activated interfaces:
Scroll Title |
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anchor | Table_PSI |
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title-alignment | center |
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title | PS Interfaces |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Note |
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DDR |
| QSPI | MIO | SD0 | MIO | SD1 | MIO | CAN0 | EMIO | I2C0 | MIO | PJTAG0 | MIO | UART0 | MIO | GPIO0 | MIO | SWDT0..1 |
| TTC0..3 |
| GEM3 | MIO | USB0 | MIO/GTP | PCIe | MIO/GTP | SATA | GTP | DisplayPort | EMIO/GTP |
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Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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language | ruby |
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title | _i_io.xdc |
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#System Controller IP
#J3:31 LED_HD
set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
#J3:41
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
#J3:45
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
#J3:47
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
#J3:32
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
#J3:34
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
#J3:36
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
#J3:38
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
#J3:40
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
#J3:42
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:46 CAN S
set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
#J3:48 LED_XMOD
set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
#J3:50 CAN TX
set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
#J3:52 CAN RX
set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
# PLL
#J4:74
#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Audio Codec
#LRCLK J3:49 B47_L9_N
#BCLK J3:51 B47_L9_P
#DAC_SDATA J3:53 B47_L7_N
#ADC_SDATA J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN H14 [get_ports I2S_bclk ]
set_property PACKAGE_PIN C13 [get_ports I2S_sdin ]
set_property PACKAGE_PIN D14 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]
# MGTs
# R8 MGT_224_CLK0_P -> B2B,J3-62 -> TEBF0808-04a_FMC_J5E-D5
# R7 MGT_224_CLK0_N -> B2B,J3-60 -> TEBF0808-04a_FMC_J5E-D4
# N8 MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
# N7 MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4
# L8 MGT_225_CLK0_P -> B2B,J3-67 -> TEBF0808-04a_FMC_J5E-B21
# L7 MGT_225_CLK0_N -> B2B,J3-65 -> TEBF0808-04a_FMC_J5E-B20
# J8 MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
# J7 MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3
# H10 MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
# H9 MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
# F10 MGT_226_CLK1_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> U5,51 -> Si5345 -> out7
# F9 MGT_226_CLK1_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> U5,50 -> Si5345 -> out7
# D10 MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
# D9 MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
# B10 MGT_227_CLK1_P -> B2B,J2-22 -> floating
# B9 MGT_227_CLK1_N -> B2B,J2-24 -> floating
set_property PACKAGE_PIN R8 [get_ports {MGT_CLK_IN_clk_p[0]}]
set_property PACKAGE_PIN N8 [get_ports {MGT_CLK_IN_clk_p[1]}]
set_property PACKAGE_PIN L8 [get_ports {MGT_CLK_IN_clk_p[2]}]
set_property PACKAGE_PIN J8 [get_ports {MGT_CLK_IN_clk_p[3]}]
set_property PACKAGE_PIN H10 [get_ports {MGT_CLK_IN_clk_p[4]}]
set_property PACKAGE_PIN F10 [get_ports {MGT_CLK_IN_clk_p[5]}]
set_property PACKAGE_PIN D10 [get_ports {MGT_CLK_IN_clk_p[6]}]
set_property PACKAGE_PIN B10 [get_ports {MGT_CLK_IN_clk_p[7]}]
# MGTs
# R8 MGT_224_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5
# R7 MGT_224_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4
# N8 MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
# N7 MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4
# L8 MGT_225_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21
# L7 MGT_225_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20
# J8 MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
# J7 MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3
# H10 MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
# H9 MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
# F10 MGT_226_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7
# F9 MGT_226_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7
# D10 MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
# D9 MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
# B10 MGT_227_CLK1_P -> B2B,J2-A6 -> floating
# B9 MGT_227_CLK1_N -> B2B,J2-A7 -> floating |
Software Design - Vitis
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System Design - Vivado
Block Design
Scroll Title |
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anchor | Figure_BD |
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title | Block Design |
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Image Removed |
PS Interfaces
Activated interfaces:
Scroll Title |
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anchor | Table_PSI |
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title | PS Interfaces |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Note |
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DDR | QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
CAN0 | EMIO |
I2C0 | MIO |
PJTAG0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 | TTC0..3 | GEM3 | MIO |
USB0 | MIO/GTP |
PCIe | MIO/GTP |
SATA | GTP |
DisplayPort | EMIO/GTP |
Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen.xdc |
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|
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Code Block |
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language | ruby |
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title | _i_io.xdc |
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|
#System Controller IP
#J3:31 LED_HD
set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
#J3:41
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
#J3:45
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
#J3:47
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
#J3:32
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
#J3:34
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
#J3:36
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
#J3:38
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
#J3:40
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
#J3:42
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:46 CAN S
set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
#J3:48 LED_XMOD
set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
#J3:50 CAN TX
set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
#J3:52 CAN RX
set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
# PLL
#J4:74
#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Audio Codec
#LRCLK J3:49 B47_L9_N
#BCLK J3:51 B47_L9_P
#DAC_SDATA J3:53 B47_L7_N
#ADC_SDATA J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports LRCLK ]
set_property PACKAGE_PIN H14 [get_ports BCLK ]
set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
|
Software Design - Vitis
For SDK Vitis project creation, follow instructions from:
Vitis
Application
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id | Comments |
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---------------------------------------------------------- FPGA Example ----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader
.c - Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2020.2 xilisf_v5_11 - Changed default Flash type to 5.
- read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2022.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: ----------------------------------------------------------Zynq Example: zynq_fsblTE modified 20202022.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2020.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20202022.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2020.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI Vitis is used to generate Boot.bin. |
SDK template in ./Template location: "<project folder>\sw_lib/\sw_apps/ available.\"zynqmp_fsbl
TE modified 20202022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI Vitis is used to generate Boot.bin.
Software Design - PetaLinux- PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Activate:
For PetaLinux installation and project creation, follow instructions from:Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0807_TEBF0808
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
I2CEEPROMGEMI2C_MAC_OFFSET=0xFA- IN_EEPROM is not set
- CONFIG_
SYSI2C_EEPROM_ADDR=0x50- RANDOM_ETHADDR is not set
- Boot Modes:SYS_I2C_EEPROM_BUS=2SYSEEPROM_SIZE256SYSEEPROMPAGE_WRITE_BITS=0
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
- IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1I2C_EEPROM_ADDR_OVERFLOW=0- REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
- IdentificationSDBOOT=y
- STRING=" TE0807_TEBF0808"
Change platform-top.h:
Device Tree
Code Block |
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language | js |
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title | project-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi |
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/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};.dtsi"
/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/
/* default */
&sata {
phy-names = "sata-phy";
phys = <&lane2 1 0 1 150000000>;
};
/* SD */
&sdhci0 {
// disable-wp;
no-1-8-v;
};
&sdhci1 {
// disable-wp;
no-1-8-v;
};
/* USB */
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
phy-names = "usb2-phy","usb3-phy";
phys = <&lane1 4 0 2 100000000>;
maximum-speed = "super-speed";
};
/* ETH PHY */
&gem3 {
phy-handle = <&phy0>;
phy0: phy0@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
/* QSPI */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
------------------ gtr --------------------*/
//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
/ {
refclk3:psgtr_dp_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <27000000>;
};
refclk2:psgtr_pcie_usb_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <100000000>;
};
refclk1:psgtr_sata_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <150000000>;
};
//refclk0:psgtr_unused_clock {
// compatible = "fixed-clock";
// #clock-cells = <0x00>;
// regclock-frequency = <0x0><100000000>;
//};
};
&psgtr {
clocks = #address-cells = <1><&refclk1 &refclk2 &refclk3>;
/* ref clk instances used per #size-cells = <1>;lane */
clock-names }= "ref1\0ref2\0ref3";
};
/* I2C */
&i2c0------------------ SD --------------------*/
&sdhci0 {
i2cswitch@73 { // udisable-wp;
no-1-8-v;
};
&sdhci1 {
compatible = "nxp,pca9548"// disable-wp;
#address-cells = <1>;
#size-cells = <0>no-1-8-v;
};
/*------------------- USB --------------------*/
&dwc3_0 {
status = "okay";
regdr_mode = <0x73>"host";
i2c-mux-idle-disconnectsnps,usb3_lpm_capable;
i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
#address-cells = <1>snps,dis_u3_susphy_quirk;
#size-cells = <0>;
snps,dis_u2_susphy_quirk;
regphy-names = <0>"usb2-phy","usb3-phy";
maximum-speed };
i2c@1 { // SFP TEBF0808 PCF8574DWR
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
= "super-speed";
};
/*------------------ ETH PHY --------------------*/
&gem3 {
/delete-property/ local-mac-address;
phy-handle = <&phy0>;
nvmem-cells = <ð0_addr>;
nvmem-cell-names = "mac-address";
phy0: phy0@1 {
}device_type = "ethernet-phy";
i2c@2reg { // PCIe= <1>;
};
};
/*----------------- SATA PHY --------------------*/
&sata {
ceva,p0-burst-params = <0x13084a06>;
ceva,p0-cominit-params #address-cells= <0x18401828>;
ceva,p0-comwake-params = <1><0x614080e>;
ceva,p0-retry-params = <0x96a43ffc>;
ceva,p1-burst-params = <0x13084a06>;
ceva,p1-cominit-params #size-cells= <0x18401828>;
ceva,p1-comwake-params = <0>;
reg<0x614080e>;
ceva,p1-retry-params = <2><0x96a43ffc>;
};
/*-------------------- i2c@3 { // SFP1 TEBF0808
QSPI ---------------------*/
&qspi {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
status = "okay";
flash0: flash@0 {
i2c@4 {// SFP2 TEBF0808
compatible = "jedec,spi-nor";
#address-cellsreg = <1><0x0>;
#size#address-cells = <0><1>;
reg #size-cells = <4><1>;
};
};
/*------------------ I2C --------------------*/
&i2c0 {
i2c@5i2cswitch@73 { // TEBF0808 EEPROM
u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
reg = <5> i2c-mux-idle-disconnect;
i2c@0 { // MCLK eeprom:TEBF0808 eeprom@50 {
SI5338A, 570FBB000290DG_unassembled
compatiblereg = "atmel,24c08"<0>;
};
reg = <0x50>;
i2c@1 { // SFP TEBF0808 PCF8574DWR
reg = }<1>;
};
i2c@6i2c@2 { // TEBF0808 FMC PCIe
#address-cellsreg = <1><2>;
};
#size-cells = <0>; i2c@3 { // SFP1 TEBF0808
reg = <6><3>;
};
i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB
#address-cellsreg = <1><4>;
};
#size-cells = <0>; i2c@5 { // TEBF0808 EEPROM
reg = <7><5>;
};
};eeprom: eeprom@50 {
i2cswitch@77 { // u
compatible = "nxpmicrochip,pca954824aa025";
#address-cells = <1>, "atmel,24c02";
#size-cells = <0>;
reg = <0x77><0x50>;
i2c-mux-idle-disconnect;
i2c@0 {
// TEBF0808 PMOD P1
#address-cells = <1>;
#size-cells = <0><1>;
reg = <0>; eth0_addr: eth-mac-addr@FA {
};
i2c@1 { //reg i2c= Audio<0xFA Codec0x06>;
#address-cells = <1>};
};
#size-cells = <0>;
};
regi2c@6 = <1>;
/*{ // TEBF0808 FMC
adau1761:reg adau1761@38= {<6>;
};
compatiblei2c@7 = "adi,adau1761";
{ // TEBF0808 USB HUB
reg = <0x38><7>;
};
};
*/
i2cswitch@77 { // };u
i2c@2compatible { // TEBF0808 Firefly A
= "nxp,pca9548";
reg = <0x77>;
#address-cells = <1> i2c-mux-idle-disconnect;
i2c@0 { // TEBF0808 #size-cells = <0>;PMOD P1
reg = <2><0>;
};
i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec
#address-cellsreg = <1>;
#size-cells = <0>;/*
regadau1761: =adau1761@38 <3>;{
};
i2c@4compatible { //Module PLL Si5338 or SI5345
= "adi,adau1761";
#address-cellsreg = <1><0x38>;
#size-cells = <0> };
reg = <4>;*/
};
i2c@5i2c@2 { // TEBF0808 Firefly CPLDA
#address-cellsreg = <1><2>;
};
#size-cells = <0>;i2c@3 { // TEBF0808 Firefly B
reg = <5><3>;
};
i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345
#address-cellsreg = <1><4>;
};
i2c@5 #size-cells = <0>;{ //TEBF0808 CPLD
reg = <6><5>;
};
i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR
#address-cellsreg = <1><6>;
};
i2c@7 { // #size-cellsTEBF0808 =PMOD <0>;P3
reg = <7>;
};
};
};
|
FSBL patch
Must be add manually, see templateKernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not set
- CONFIG_EDAC_CORTEX_ARM64=y
- # CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not set
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set
- # CONFIG_NVME_TCP is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME
_TARGET_TCP is not set - CONFIG_NVM=y
- _TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- For additional test tools only:CONFIG_NVM_PBLKNVM_PBLK_DEBUG=y
- CONFIG_EDAC_CORTEX_ARM64=y
- packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:CONFIG_SATA_AHCISATAMOBILELPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
- USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
Note |
---|
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
Applications
See "<project folder>See: \os\petalinux\project-spec\meta-user\recipes-apps\
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for ZynqMP access. Need busybox-httpd
Additional Software
Scroll Ignore |
---|
scroll-pdf | true |
---|
scroll-office | true |
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scroll-chm | true |
---|
scroll-docbook | true |
---|
scroll-eclipsehelp | true |
---|
scroll-epub | true |
---|
scroll-html | true |
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|
Additional Software
Page properties |
---|
|
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
SI5345
File location <design name>/misc/Si5345/"<project folder>\misc\PLL\Si5345_B\Si5345-*.slabtimeproj
General documentation how you work with these project will be available on Si5345
"
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
Scroll Ignore |
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scroll-pdf | true |
---|
scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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|
Appx. A: Change History and Legal NoticesDocument Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties |
---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Scroll Title |
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anchor | Table_dch |
---|
title | Document change history. |
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|
Scroll Table Layout |
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orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | 2*,*,3*,4* |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Document Revision | Authors | Description |
---|
Page info |
---|
infoType | Modified date |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
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|
| Page info |
---|
infoType | Current version |
---|
prefix | v. |
---|
type | Flat |
---|
|
| Page info |
---|
infoType | Modified by |
---|
type | Flat |
---|
|
| - 2022.2 update
- new assembly variants
| 2022-10-17 | v.27 | Manuela Strücker | | 2022-09-12 | v.26 | Manuela Strücker | - update board part files compatible to Vivado 2021.2.1
| 2022-09-12 | v.25 | Manuela Strücker | - 2021.2 update
- new assembly variants
- update document style
| 2021-05-11 | v.23 | Martin Rohrmüller | - 2020.2 release
- document style update
| 2020-10-06 | v.21 | John Hartfiel | | 2020-03-25 | v.20 | John Hartfiel | | 2020-02-25 | v.19 | John Hartfiel | | requiroment | 2020-02-19 | v.18 | John Hartfiel | | 2020-01-27 | v.17 | John Hartfiel | - new assembly variants
- Release 2019.2
| 2019-05-22 | v.16 | John Hartfiel | | | v.13 | John Hartfiel | | | v.12 | John Hartfiel | | | v.10 | John Hartfiel | | | v.9 | John Hartfiel | | 2018-01-29 | v.4 | John Hartfiel | | 2018-01-18 | v.3 | John Hartfiel | |
| All | Page info |
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infoType | Modified users |
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type | Flat |
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|
|
|
|
Legal Notices
Include Page |
---|
| IN:Legal Notices |
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| IN:Legal Notices |
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|