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Table 3: Zynq SoC PL I/O signals overview.

JTAG Interface

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Quad SPI Flash (U5) is connected to the Zynq SoC PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 35: Quad SPI interface signals and connections.

SD Card Interface

TE0723 TE0722 module has on-board 3.3V SD Card socket (J10J8) with card detect switch wired to the Zynq SoC PS MIO bank 500501, pins MIO28 .. MIO33 and MIO49.

Table 46: SD card socket interface signals.

I2C Interface

I²C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Table 7: Zynq SoC I²C interface.

I2C Interface

I²C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Table 7: Zynq SoC I²C interface signals.

Default PS MIO Mapping

 Table 58: .

On-board Peripherals

Quad SPI Flash Memory

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Table 69: .

Power and Power-On Sequence

Power Consumption

Power supply with minimum current capability of 1A for system startup is recommended. The maximum power consumption of the module mainly depends on the design running on the Zynq SoC's FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It is also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 7: Typical power consumption is to be determined.

 * TBD - To Be Determined.

Power supply with minimum current capability of 1A for system startup is recommended.

Power-On Sequence

... diagram will be here soon ...

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