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General instructions

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CPLD

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CPLD Access  

Set B2B Pin JM1-89 (JTAGEN) to VDD (3.3V)

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1. Connect MiniUSB cable to XMOD
2. Set DIP Switch S1-2 to OFF position, see TE0706 TRM#4-bitDIP-switch
3. Power ON the board
4. Run "Lattice Diamond Programmer"

5. Select "Create new project from JTAG chain" and press "OK"

Available CPLD Firmware

• TE0720 CPLD - Firmware description (working in process)for different PCB versions and variants
  • CPLD firmware REV07 for PCB REV02 , REV03 and REV04 :
    
    • For all module variants as default variant located in "SC-PGM-TE0720-0304_XO2E-07_20220628" folder (Default) 
      • QSPI/JTAG/SD boot modes and PUDC = 0
    • For all module variants located in "SC-PGM-TE0720-0304_XO2E-07_20220628/optional"  folder (Optional)
      • QSPI/JTAG/SD boot modes and PUDC = 1
      • QSPI/SD boot modes and PUDC = 0
      • QSPI/SD boot modes and PUDC = 1
      • QSPI/JTAG boot modes and PUDC = 0
      • QSPI/JTAG boot modes and PUDC = 1
      • JTAG/SD boot modes and PUDC = 0
      • JTAG/SD boot modes and PUDC = 1

Download

• TE0720/<PCB Revision>/Firmware/
  • Use files from the subfolders of your PCB revision

General instructions