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Si5338A Pin	Signal Name / Description	Connected To	Direction	Note
IN1	-	Not not connected.	Input	Not not used.
IN2	-	GND	Input	Not not used.
IN3	Reference input clock.	U3, pin 3	Input	25.000000 MHz oscillator, Si8208AI.
IN4	-	GND	Input	I²C slave device address LSB.
IN5	-	Not not connected.	Input	Not not used.
IN6	-	GND	Input	Not not used.
CLK0A	CLK1_P	U1, R23	Output	FPGA bank 45.
CLK0B	CLK1_N	U1, P23	Output	FPGA bank 45.	Output
CLK1A	MGT_CLK1_N	U1, V5	Output	FPGA MGT bank 225 reference clock.
CLK1B	MGT_CLK1_P	U1, V6Output	Output	FPGA MGT bank 225 reference clock.
CLK2A	MGT_CLK3_N	U1, AB5	Output	FPGA MGT bank 224 reference clock.
CLK2B	MGT_CLK3_P	U1, AB6Output	Output	FPGA MGT bank 224 reference clock.
CLK3A	CLK0_P	U1, pin T24	Output	FPGA bank 45.
CLK3B	CLK0_N	U1, pin T25	Output	FPGA bank 45.	Output

Table 8: Programmable quad PLL clock generator inputs and outputs.

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Board to Board Connectors

Include Page

	PD:4 x 5 SoM LSHM B2B ConnectorsPD:
	4 x 5 SoM LSHM B2B Connectors

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