Table of Contents
The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 1 GByte of DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.
- Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
- 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
- 256 Mbit (32 MByte) QSPI Flash
- 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- 60 x HR I/Os
- 84 x HP I/Os
- 8 x GTH transceiver lanes (TX/RX)
- 2 x MGT external clock inputs
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator
- All power supplies on-board, single power source operation
- Evenly spread supply pins for optimized signal integrity
- Size: 40 x 50 mm
- 3 mm mounting holes for skyline heat spreader
- Rugged for industrial applications
Additional assembly options for cost or performance optimization plus high volume prices are available on request.
Figure 1: TE0841-01 block diagram.
Figure 2: TE0841-01 main components.
- Xilinx Kintex UltraScale FPGA, U1
- Ultra performance oscillator @25.000000 MHz, U3
- 12A PowerSoC DC-DC converter (0.95V), U14
- 12A PowerSoC DC-DC converter (0.95V), U7
- Low-jitter precision LVDS oscillator @200.0000 MHz, U11
- Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
- Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
- Samtec Razor Beam™ LSHM-150 B2B connector, JM1
- Samtec Razor Beam™ LSHM-150 B2B connector, JM2
- Samtec Razor Beam™ LSHM-130 B2B connector, JM3
- Programmable quad clock generator, U2
- 32 MByte QSPI Flash, U6
- 4 Gbit DDR4 SDRAM, U4
- 4 Gbit DDR4 SDRAM, U5
- System Controller CPLD, U18
- Low-dropout (LDO) linear regulator (MGTAUX), U9
- Ultra-low power low-dropout (LDO) regulator (VBATT), U19
Initial Delivery State
Storage device name
|System Controller CPLD||Default firmware||-|
Quad SPI Flash OTP area
|Quad clock generator OTP area||Empty||Not programmed|
Table 1: TE0841-01 module initial delivery state of programmable on-board devices.
By default the configuration mode pins of the FPGA are set to QSPI mode, hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
Table below lists bank number, bank type, B2B connection, I/O signal/LVDS pair count and power source for each FPGA PL I/O bank connected to the B2B connectors:
|FPGA Bank||Type||B2B Connector||I/O Signal Count||Voltage||Notes|
|64||HR||JM1||48 IOs, 24 LVDS pairs||B64_VCCO||Supplied by the carrier board|
|65||HR||JM1||8 IOs||3.3V||On-module power supply|
|65||HR||JM3||4 IOs, 2 LVDS pairs||3.3V||On-module power supply|
|66||HP||JM3||16 IOs, 8 LVDS pairs||B66_VCCO||Supplied by the carrier board|
|67||HP||JM2||48 IOs, 24 LVDS pairs||B67_VCCO||Supplied by the carrier board|
|67||HP||JM2||2 IOs||B67_VCCO||Supplied by the carrier board|
|68||HP||JM2||18 IOs, 9 LVDS pairs||B68_VCCO||Supplied by the carrier board|
Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.
For detailed information about the pin out, please refer to the Pin-out Tables.
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pin connection information:
|Lane||Bank||Type||Signal Name||B2B Pin||FPGA Pin|
Table 3: FPGA to B2B connectors routed MGT lanes overview.
Below are listed MGT banks reference clock sources.
|Clock signal||Bank||Source||FPGA Pin||Notes|
|MGT_CLK0_P||225||B2B, JM3-33||MGTREFCLK0P_225, Y6||Supplied by the carrier board.|
|MGT_CLK0_N||B2B, JM3-31||MGTREFCLK0N_225, Y5|
|MGT_CLK1_P||225||U2, CLK1B||MGTREFCLK1P_225, V6||On-board Si5338A.|
|MGT_CLK1_N||U2, CLK1A||MGTREFCLK1N_225, V5|
|MGT_CLK2_P||224||B2B, JM3-34||MGTREFCLK2P_224, AD6||Supplied by the carrier board.|
|MGT_CLK2_N||B2B, JM3-32||MGTREFCLK2N_224, AD5|
|MGT_CLK3_P||224||U2, CLK2B||MGTREFCLK3P_224, AB6||On-board Si5338A.|
|MGT_CLK3_N||U2, CLK2B||MGTREFCLK3N_224, AB5|
Table 4: MGT banks reference clock sources.
JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.
B2B Connector Pin
Table 5: JTAG interface signals.
System Controller CPLD I/O Pins
Special purpose pins are connected to the System Controller CPLD and have following default configuration:
|Pin Name||Mode||Function||Default Configuration|
|JTAGMODE||Input||JTAG select||Low for normal operation.|
|SC1||-||-||Not used by default.|
|SC2||-||-||Not used by default.|
|SC3||-||-||Not used by default.|
|SC4||-||-||Not used by default.|
Table 6: System Controller CPLD I/O pins.
Quad SPI Interface
Quad SPI interface is connected to the FPGA configuration bank 0.
|Signal Name||QSPI Flash Memory U6 Pin||FPGA Pin|
Table 7: Quad SPI interface signals and connections.
There are two PL bank 65 I/O pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
Additionally, two PL bank 65 I/O pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary I/Os.
System Controller CPLD
The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
By default TE0841 module has two NT5AD256M16 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Programmable Clock Genetraor
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate several reference clocks for the module.
|Si5338A Pin||Signal Name / Description||Connected To||Direction||Note|
Reference input clock.
|U3, pin 3||Input||25.000000 MHz oscillator, Si8208AI.|
|-||GND||Input||I2C slave device address LSB.|
|Not connected.||Input||Not used.|
FPGA bank 45.
|CLK1A||MGT_CLK1_N||U1, V5||Output||FPGA MGT bank 225 reference clock.|
|CLK2A||MGT_CLK3_N||U1, AB5||Output||FPGA MGT bank 224 reference clock.|
|U1, pin T24||Output|
FPGA bank 45.
|CLK3B||CLK0_N||U1, pin T25||Output|
Table 8: Programmable quad PLL clock generator inputs and outputs.
The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
|Clock Source||Frequency||Signal Name||Clock Destination|
|U3, SiT8208AI||25.000000 MHz||CLK||U2, pin 3 (IN3)|
|U11, DSC1123DL5||200.0000 MHz||CLK200M_P||U1, pin R25|
|CLK200M_N||U1, pin R26|
|B2B, JM3-31||User||MGT_CLK0_N||U1, pin Y5|
|B2B, JM3-33||MGT_CLK0_P||U1, pin Y6|
|B2B, JM3-32||User||MGT_CLK2_N||U1, pin AD5|
|B2B, JM3-34||MGT_CLK2_P||U1, pin AD6|
Table 9: Reference clock signals.
|LED||Color||Connected to||Description and Notes|
|D1||Green||System Controller CPLD, bank 3||Exact function is defined by SC CPLD firmware.|
Table 10: On-board LEDs.
Power and Power-On Sequence
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
|Power Input||Typical Current|
Table 11: Typical power consumption.
* TBD - To Be Determined.
Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
For the highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously. It is important that all I/Os of the carrier board are 3-stated at the beginning of the power-on cycle until 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module PL supply voltages have become stable and Zynq MPSoC module is powered up properly.
Figure 3: TE0841-01 Power-on sequence.
See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0841 module.
|Power Rail Name|
B2B JM1 Pins
B2B JM2 Pins
|VIN||1, 3, 5||2, 4, 6, 8||Input||Supply voltage.|
|3.3VIN||13, 15||-||Input||Supply voltage.|
|B64_VCO||9, 11||-||Input||HR (High Range) bank voltage.|
|B66_VCO||-||1, 3||Input||HP (High Performance) bank voltage.|
|B67_VCO||-||7, 9||Input||HP (High Performance) bank voltage.|
|B68_VCO||-||5||Input||HP (High Performance) bank voltage.|
|79||-||Input||RTC battery supply voltage.|
|3.3V||-||10, 12, 91||Output||Module on-board 3.3V voltage level.|
Table 12: Module power rails.
|44 HP||DDR_1V2||1.2V||HP: 1.2V to 1.8V|
|45 HP||PL_1.8V||1.8V||HP: 1.2V to 1.8V|
|46 HP||DDR_1V2||1.2V||HP: 1.2V to 1.8V|
|64 HR||B64_VCO||user||HR: 1.2V to 3.3V|
|65 HR||3.3V||3.3V||HR: 1.2V to 3.3V|
|66 HP||B66_VCO||user||HP: 1.2V to 1.8V|
|67 HP||B67_VCO||user||HP: 1.2V to 1.8V|
|68 HP||B68_VCO||user||HP: 1.2V to 1.8V|
Table 13: Module's bank voltages.
Board to Board Connectors
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
- 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
- 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
|Order number||Connector on baseboard||compatible to||Mating height|
The module can be manufactured using other connectors upon request.
Connector Speed Ratings
The LSHM connector speed rating depends on the stacking height; please see the following table:
|Stacking height||Speed rating|
|12 mm, Single-Ended||7.5 GHz / 15 Gbps|
|12 mm, Differential|
6.5 GHz / 13 Gbps
|5 mm, Single-Ended||11.5 GHz / 23 Gbps|
|5 mm, Differential||7.0 GHz / 14 Gbps|
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
Variants Currently In Production
Table 14: Module variants in production.
Absolute Maximum Ratings
VIN supply voltage
|EN63A0QI, TPS74401RGW datasheets.|
|3.3VIN supply voltage||-0.1||3.75||V||TPS27082, LCMXO2-256HC datasheets.|
|Supply voltage for HR I/O banks (VCCO)|
|V||Xilinx datasheet DS892.|
Supply voltage for HP I/O banks (VCCO)
|2.000||V||Xilinx datasheet DS892.|
|I/O input voltage for HR I/O banks|
VCCO + 0.550
|V||Xilinx datasheet DS892.|
I/O input voltage for HP I/O banks
VCCO + 0.550
|V||Xilinx datasheet DS892.|
|GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)||-0.500||1.320||V||Xilinx datasheet DS892.|
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
|V||Xilinx datasheet DS892.|
Table 15: Module absolute maximum ratings.
Recommended Operating Conditions
|VIN supply voltage||3.3||5.5||V||TPS82085SIL, TPS74401RGW datasheet|
|3.3VIN supply voltage||2.375||3.6||V||LCMXO2-256HC datasheet|
|Supply voltage for HR I/O banks (VCCO)||1.140|
|V||Xilinx datasheet DS892|
Supply voltage for HP I/O banks (VCCO)
|V||Xilinx datasheet DS892|
I/O input voltage
|VCCO + 0.20||V||Xilinx datasheet DS892|
Table 16: Module recommended operating conditions.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure 4: Module physical dimensions.
Hardware Revision History
First production revision
Table 17: Hardware revision history.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Figure 5: Module hardware revision number.
Document Change History
Jan Kumann, Ali Naseri
Table 18: Document change history.
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