Page History

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1. MAX10 FPGA, U5
2. Programmable low jitter clock generator Si5354A, U2
3. Status LED (green), D1
4. 3.3V to 1.8V DCDC converter, U6
5. Quad SFP+ cage and connectors, J4-J7
6. 1x6 pin header for JTAG programming of FPGA (3.3V), J3
7. 1x3 pin header for I²C (1.8V), J1
8. XTAL 54.0000 MHz (CX3225SB), Y1
9. Oszillator 25.000000 MHz (SiT8008B), U1
10. HPC FMC connector, J2
11. 128KBit EEPROM, U4
12. Testpoints Max10, TP7-TP9
13. Testpoints JTAG, TP1-TP4
14. Testpoints Power, TP5, TP6, TP10

Initial Delivery State

Table 2: Initial delivery state of programmable devices on the module.

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I/O signals connected to the FPGA I/O bank and B2B connector: 

Table 3: General overview of I/O signals connected to the B2B connectors.

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TD/RD) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, and HPC FMC Pin:

Table 4: MGT lanes.

Below are listed MGT banks reference clock sources.

Table 5: MGT reference clock sources.

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JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.

Table 6: JTAG interface signals.

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On-board I²C devices are connected to the HPC FMC Pin C30 SCL and pin C31 SDA which are reserved for I²C. Level shift and for PLL and SFP+ I²C is done by the FPGA as well as MUX for SFP+. Addresses for on-board devices are listed in the table below:

Table 7: I²C slave device addresses.

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There is a Silicon Labs I²C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module.

Not connected.

 Table 8: Programmable quad PLL clock generator inputs and outputs.

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 9: Reference clock signals.

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A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

On-board LEDs

Table 10: On-board LEDs.

Power and Power-On Sequence

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The maximum power consumption of a module mainly depends on the design running on the FPGA.Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 11: Typical power consumption.

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Figure 3: Module power distribution diagram.

Power Rails

Table 12: Module power rails.

Bank Voltages

Table 13: Module PL I/O bank voltages.

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Variants Currently In Production

Table 14: Module variants.

Technical Specifications

Absolute Maximum Ratings

Table 15: Module absolute maximum ratings.

Recommended Operating Conditions

Table 16: Module recommended operating conditions.

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Hardware Revision History

Table 17: Module hardware revision history.

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Table 18: Document change history.

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