Page History

...

Table 5: MGT reference clock sources.

Follwowing table contains a brief description of the control and status signals of the SFP+ connectors:

Signal Schematic Name	FPGA Direction	Description	Logic
SFPx_TX_DISABLE	Output	SFP Enabled / Disabled	Low active
SFPx_LOS	Input	Loss of receiver signal	High active
SFPx_RS0	Output	Full RX bandwidth	Low active
SFPx_RS1	Output	Reduced RX bandwidth	Low active
SFPx_M-DEF0	Input	Module present / not present	Low active
SFPx_TX_FAULT	Input	Fault / Normal Operation	High active
SFPx_SDA	BiDir	2-wire Serial Interface Data	-
SFPx_SCL	Output	2-wire Serial Interface Clock	-

Note
SCL signal is Master driven only, therefore clockstreching is not allowed.

JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.

...

I²C Device	I2C Address	Notes
J4, SFP+		1100010	SFP Device select via MAX10 FPGA implementation.
J5, SFP+	1100010	SFP Device select via MAX10 FPGA implementation.
J6, SFP+	1100010	SFP Device select via MAX10 FPGA implementation.
J7, SFP+	1100010	SFP Device select via MAX10 FPGA implementation.
U2, Si5345A	1101001	Level shifted via MAX10 FPGA
U4, EEPROM	10100xx	Last digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1).

...

Note
Mounting holes near the front pannel are not implemented due to physical restrictions caused by the SFP cage, not implemented. The dimensions exceed in some area the by Vita 57.1 standard defined dimensions. In the middle region of the card the cage is higher than the specified max high for this area. The bottom side is at the high limit.

...

Versions Compared