Table of Contents
Overview
The Trenz Electronic TEF0008 is a FPGA to Mezzanine Card (FMC) based on VITA 57.1 FMC HPC Standard, with four SFP+ 10Gb fiber optical (850nm) ports. It is inteded for use on a FMC HPC carrier and can not be used stand-alone.
Key Features
- Four SFP+ 10Gb (850nm) ports
- HPC FMC connector
- Low jitter programmable clock generator
- Intel(Altera) Max10 FPGA 10M08SAU169C8G
- Status LED (green)
Block Diagram
Figure 1: TEF0008-01 block diagram.
Main Components
Figure 2: TEF0008-01 FMC overview.
Table 1: TEF0008-01 main components.
- MAX10 FPGA, U5
- Programmable low jitter clock generator Si5354A, U2
- Status LED (green), D1
- 3.3V to 1.8V DCDC converter, U6
- Quad SFP+ cage and connectors, J4-J7
- 1x6 pin header for JTAG programming of FPGA (3.3V), J3
- 1x3 pin header for I²C (1.8V), J1
- XTAL 54.0000 MHz (CX3225SB), Y1
- Oszillator 25.000000 MHz (SiT8008B), U1
- HPC FMC connector, J2
- 128KBit EEPROM, U4
- Testpoints Max10, TP7-TP9
- Testpoints JTAG, TP1-TP4
- Testpoints Power, TP5, TP6, TP10
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
Max10 FPGA | .. | .. |
| Clock generator | .. | .. |
| EEPROM | .. | .. |
Table 2: Initial delivery state of programmable devices on the module.
Boot Process
The MAX10 FPGA boots form its internal configuration flash memory, which is programmable via JTAG.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the FPGA I/O bank and B2B connector:
| Bank | Type | B2B Connector | I/O Signal Count | Bank Voltage | Notes |
|---|---|---|---|---|---|
| 3 | GPI/Os | J2 | 20 I/Os | VADJ | Supplied by the carrier board. |
Table 3: General overview of I/O signals connected to the B2B connectors.
MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TD/RD) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, and HPC FMC Pin:
| Lane | SFP+ | Signal Name | HPC FMC Pin |
|---|---|---|---|
| 0 | J4 |
|
|
| 1 | J5 |
|
|
| 2 | J6 |
|
|
| 3 | J7 |
|
|
Table 4: MGT lanes.
Below are listed MGT banks reference clock sources.
| Clock signal | Source | HPC FMC Pin | Notes |
|---|---|---|---|
| GBTCLK0_P | U2-51 | J2-D4, GBTCLK0_M2C_P | On-board Si5345A. |
| GBTCLK0_N | U2-50 | J2-D5, GBTCLK0_M2C_N | On-board Si5345A. |
| GBTCLK1_P | U2-31 | J2-B20, GBTCLK1_M2C_P | On-board Si5345A. |
| GBTCLK1_N | U2-30 | J2-B21, GBTCLK1_M2C_N | On-board Si5345A. |
Table 5: MGT reference clock sources.
JTAG Interface
JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.
JTAG Signal | HPC FMC Pin | Pin Header | Testpoints |
|---|---|---|---|
| TCK | J2-D29 | J3-4 | TP2 |
| TDI | J2-D33 | J3-2 | TP1 |
| TDO | J2-D30 | J3-3 | TP3 |
| TMS | J2-D31 | J3-1 | TP4 |
Table 6: JTAG interface signals.
I2C Interface
On-board I2C devices are connected to the HPC FMC Pin C30 SCL and pin C31 SDA which are reserved for I2C. Level shift and for PLL and SFP+ I²C is done by the FPGA as well as MUX for SFP+. Addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|---|---|
| J4, SFP+ | ||
| J5, SFP+ | ||
| J6, SFP+ | ||
| J7, SFP+ | ||
| U2, Si5345A | 1101001 | Level shifted via MAX10 FPGA |
| U4, EEPROM | 10100xx | Last digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1). |
Table 7: I2C slave device addresses.
On-board Peripherals
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module.
Not connected.
| Si5345A Pin | Signal Name / Description | Connected To | Direction | Note |
|---|---|---|---|---|
IN0 | Reference input clock. | U1 | Input | 25.000000 MHz oscillator, Si8208AI |
| IN1 | - | Not connected. | Input | Not used. |
IN2 | - | Not connected. | Input | Not used. |
IN3 | CLK2 | J2-K4/K5 | Input | HPC FMC configured as C2M clock. |
A1 | - | GND | Input | I2C slave device address LSB. |
| XAXB | - | Y1 | Input | 54.0000 MHz XTAL CX3225SB |
OUT0 | CLKPLL2F | U5-H6/G5 | Output | FPGA bank 2. |
| OUT1 | - | Not connected. | Output | Not used. |
| OUT2 | GBTCLK1 | J2-B20/B21 | Output | M2C via HPC FMC. |
| OUT3 | - | Not connected. | Output | Not used. |
| OUT4 | - | Not connected. | Output | Not used. |
| OUT5 | - | Not connected. | Output | Not used. |
| OUT6 | - | Not connected. | Output | Not used. |
| OUT7 | GBTCLK0 | J2-D4/D5 | Output | M2C via HPC FMC. |
| OUT8 | CLK0 | J2-H4/H5 | Output | M2C via HPC FMC. |
| OUT9 | CLK1 | J2-G2/G3 | Output | M2C via HPC FMC. |
Table 8: Programmable clock generator inputs and outputs.
Oscillators
The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
| Clock Source | Schematic Name | Frequency | Clock Destination |
|---|---|---|---|
| SiTime SiT8008AI oscillator, U1 | - | 25.000000 MHz | U2-63/64 |
| Carrier board via HPC FMC J2-K4/K5 | CLK2 | Defined by carrier. | U2-61/62 |
Table 9: Reference clock signals.
EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | U5-C2 (bank 1A) | Status LED: ... |
Table 10: On-board LEDs.
Power and Power-On Sequence
Power Consumption
The maximum power consumption of a module depends on the design running on the FPGA.
| 3P3V | TBD* |
| VADJ (at 1.8V) | TBD* |
3P3VAUX | TBD* |
Table 11: Typical power consumption.
* TBD - To Be Determined with reference design setup.
Power Distribution Dependencies
Regulator dependencies and max. current.
Figure 3: Module power distribution diagram.
Power Rails
Power Rail Name | HPC FMC Connector (J2) | Direction | Notes |
|---|---|---|---|
| 3P3V | D36, D38, D40, C39 | Input | Supply voltage from carrier board. |
| 1.8V | - | Output | Module on-board 1.8V voltage supply (Max 1A). |
| 3P3VAUX | D32 | Input | Supply voltage from carrier board. |
VADJ | H40, G39, F40, E39 | Input | Supply voltage from carrier board. |
| 12V | C35, C37 | Input | Not used supply voltage from carrier board. |
Table 12: Module power rails.
Bank Voltages
Bank | Schematic Name | Voltage | Voltage Range |
|---|---|---|---|
| 1A | 3P3V | 3.3V | - |
| 1B | 3P3V | 3.3V | - |
| 2 | 1.8V | 1.8V | - |
| 3 | VADJ | Carrier supplied | 1.2V - 3.3V |
| 5 | 3P3V | 3.3V | - |
| 6 | 3P3V | 3.3V | - |
| 8 | 3P3V | 3.3V | - |
Table 13: Module PL I/O bank voltages.
Variants Currently In Production
| Module Variant | FPGA | Operating Temperature | Temperature Range |
|---|---|---|---|
| TE0008-01 | 10M08SAU169C8G | 0°C to +70°C | Commercial |
Table 14: Module variants.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature |
| °C | - |
Table 15: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | ||||
| Operating temperature |
Table 16: Module recommended operating conditions.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Physical Dimensions
Module size: 69 mm × 84 mm, SFP+ conector excluded (+ 5.5 mm). See Vita 57.1 standard.
PCB thickness: 1.6 mm.
Highest part on PCB top is 9.5 mm (SFP+ cage, excluded front plate), bottom 1.4 mm (MAX10 FPGA). Please download the step model for exact numbers.
All dimensions are given in millimeters.
Put mechanical drawings here...
Figure : Module physical dimensions drawing.
Mounting holes near the front pannel are due to physical restrictions caused by the cage, not implemented. The dimensions exceed in some area the by Vita 57.1 standard defined dimensions. In the middle region of the card the cage is higher than the specified max high for this area. The bottom side is at the high limit.
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 |
Table 17: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Figure 4: Module hardware revision number.
Document Change History
Date | Revision | Contributors | Description |
|---|---|---|---|
| Author Name | What changed? | ||
Martin Rohrmüller | Initial document. | ||
all | Jan Kumann, John Hartfiel |
Table 18: Document change history.
Disclaimer
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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