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Excerpt
PetaLinux MicroBlaze SRECI2CI2C UART Flash MIG FMeter SI5338 initialisation with MCS ETH

Revision History

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Date	Vivado	Project Built	Authors	Description
2018-04-

122017.4te0712-test_board-vivado_2017.4-build_07_20180412081225.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip

16

2017.4

John Hartfiel

Bugfix Constrain File - ETH REFCLK, Timing

2018-03-282017.4te0712-test_board-vivado_2017.4-build_07_20180328145151.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zipJohn Hartfiel

new assembly variant

2018-01-082017.4te0712-test_board-vivado_2017.4-build_02_20180108155712.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zipJohn Hartfiel

No Design changes
small constrain changes

2017-12-152017.2te0712-test_board-vivado_2017.2-build_07_20171215172447.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zipJohn Hartfiel

Add SI5338 initialisation with MCS
Add Ethernet IP

2017-11-072017.2te0712-test_board-vivado_2017.2-build_05_20171107172917.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zipJohn Hartfiel

Add Wiki Link in Boart Part Files
Set Correct Short Link for te0712-02-200-2c

2017-10-052017.2te0712-test_board-vivado_2017.2-build_03_20171005082148.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zipJohn Hartfiel

initial release

Release Notes and Know Issues

initial release

Release Notes and Know Issues

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Issues	Description	Workaround	To be fixed version

For PCB REV01 only: CLK1B is not available onaddtional clk is not connected on PCBuse other internal generated CLK, maybe mor effort is needed to get ETH running


---	---	---	---

SREC SPI BootLoader default Offset

Default load offset is set to 0x400000Change manually on SDK to 0x5E0000next update

Requirements

Software

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Software	Version	Note
Vivado	2017.4	needed
SDK	2017.4	needed

PetaLinux2017.4needed

Hardware

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Design supports following modules:

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others	Notes

te0712

TE0741-

02

03-

35

070-

2i

2IF

35

070_

2i

2if	REV02, REV03

1GB32MBte0712-02-100-1i 100_1i REV01, REV021GB32MBte0712-02-100-2c100_2c REV01, REV021GB32MBte0712-02-100-2c3

100_2c

REV01, REV021GB32MB2,5 mm connectorte0712-02-100-2ca

100_2ca

REV021GB32MBMicron QSPI Flash

---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-160-2IF	160_2if	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-325-2IF	325_2if	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-410-2IF	410_2if	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-070-2CF	070_2cf	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-160-2CF	160_2cf	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-325-2CF	325_2cf	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-410-2CF	410_2cf	REV02, REV03	---	32MB	MGT LR: 6,6 Gb/s
TE0741-03-160-2C1	160_2c1	REV02, REV03	---	32MB	MGT LR: 10,3125 Gb/s

te0712-02-200-1i200_1i REV01, REV021GB32MB

te0712-02-200-1i3

200_1i

REV01, REV021GB32MB2,5 mm connectorte0712-02-200-2i 200_2i REV01, REV021GB32MBte0712-02-200-2c200_2cREV01, REV021GB32MBte0712-02-200-2c3200_2cREV01, REV021GB32MB2,5 mm connector

Design supports following carriers:

Carrier Model	Notes
TE0701
TE0703	used as reference carrier
TE0705
TE0706
TEBA0841

Additional HW Requirements:

Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct typ
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware	Vivado Project will be generated by TE Scripts
SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux	<design name>/os/petalinux	PetaLinux template with current configuration

Additional Sources

Type	Location	Notes
SI5338 Project	\misc\SI5338

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File	File-Extension	Description
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Date

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Authors

Description

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dateFormat	yyyy-MM-dd

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Know Issues
Documentation

12 Apr 2018

v.23

John Hartfiel

Design Update

28 Mar 2018

v.22

John Hartfiel

Know Issue for PCB REV01 only
fix typo
new assembly variant

2018-02-13

v.19

John Hartfiel

Release 2017.4

2018-01-08

v.16

John Hartfiel

Add SCU source path

2017-12-15

v.15

John Hartfiel

Update Design and Description

2017-11-07

v.11

John Hartfiel

Update Design Files

2017-10-06

v.10

John Hartfiel

small Document Update

2017-10-05

v.8

John Hartfiel

Release 2017.2

2017-09-11

v.1

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Initial release

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Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 2

New Version 3

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Revision History

Release Notes and Know Issues

Release Notes and Know Issues

Requirements

Software

Hardware

Content

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