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| Switch | Signal Name | ON | OFF | Notes |
|---|---|---|---|---|
| S1-1 | - | - | - | Not connected. |
| S1-2 | PROGMODE | JTAG enabled for programing mounted SoM's Zynq-SoC. | JTAG enabled for programing mounted SoM's SC-CPLD. | - |
| S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low. (SD-Boot) | Leave SoM SC CPLD pin 'MODE' open. (QSPI-Boot) | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware). |
| S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low. | Drive SoM SC CPLD pin 'EN1' high. | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM. |
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Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| John Hartfiel |
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| 2017-11-10 | v.64 | John Hartfiel |
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| 2017-11-09 | v.60 | Ali Naseri |
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2017-07-06 | v.52 | Ali Naseri, Jan Kumann |
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| 2017-01-06 | v.1 | Ali Naseri |
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