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Table of Contents

Table of Contents

Overview

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The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.

Key Features

Single 24V main power supply
Motherboard fitted to dedicated enclosure from Trenz ??
2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
Gigabit Ethernet RGMII PHY with RJ45 MegJack
Dual SFP+ Connector (2x1 Cage)
DDR4-SDRAM SODIMM socket (64bit bus width)
SSD (Solid State Disk) Connector
CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
1x DisplayPort
4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
6x FMC HPC Connectors
6x FMC Fans
3x Optional 4-wire PWM fan connectors
10 output programmable PLL clock generator Si5345A
Quad programmable PLL clock generator SI5338A
1x SMA coaxial connectors for reference clock signal input
MicroSD-Socket (bootable)
32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
System Controller CPLD Lattice MachXO2 7000 HC
2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
On-board DC-DC PowerSoCs and LDOs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Put your block diagram here...

Figure 1: TE0xxx-xx block diagram.

Main Components

Put top and bottom pics with labels of the real PCB here...

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Add description list of PCB labels here...

Initial Delivery State

Storage device name	Content	Notes
User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
USB3.0 HUB Configuration EEPROM (Microchip 24LC128-I/ST)	Empty	Not programmed
Si5338A programmable PLL NVM OTP
Si5345A programmable PLL NVM OTP

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

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Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.

Signals, Interfaces and Pins

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FMC Connectors

The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.

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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:

Anchor

	testFMC A	test

TEB0911 UltraRack TRM

	FMC A

FMC A

FMC A Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J10 (FMC A)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
	I/O	46	28	SC CPLD U27 Bank 1	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 128 GTH	-	4x MGT lanes
	Clock Input	-	1	Bank 128 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

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Table 7: FMC A connector cooling fan

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	FMC F
	FMC F

FMC F

FMC F Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J21 (FMC F)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
		28	14	SC CPLD U27 Bank 1	FMCAF_1V8	-
		68	34	SC CPLD U27 Bank 3	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	4 (2 x RX/TX)	Bank 129 GTH	-	2x MGT lanes
	Clock Input	-	1	Bank 129 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'

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Table 12: FMC F connector cooling fan

Anchor

	FMC B
	FMC B

FMC B

FMC B Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J4 (FMC B)	I/O	24	12	Bank 47 HD	FMCBC_1V8	-
		20	10	Bank 48 HD	FMCBC_1V8	-
		24	12	Bank 49 HD	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 0	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 130 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 48 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 130 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

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Table 17: FMC B connector cooling fan

Anchor

	FMC C
	FMC C

FMC C

FMC C Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J8 (FMC C)	I/O	20	10	Bank 50 HD	FMCBC_1V8	-
	I/O	68	34	Bank 67 HP	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 230 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 50 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 230 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

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Table 22: FMC C connector cooling fan

Anchor

	FMC D
	FMC D

FMC D

FMC D Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J7 (FMC D)	I/O	20	10	Bank 65 HP	FMCDE_1V8	-
	I/O	48	24	Bank 66 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 229 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 65 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 229 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

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Table 27: FMC D connector cooling fan

Anchor

	FMC E
	FMC E

FMC E

FMC E Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J6 (FMC E)	I/O	24	12	Bank 65 HP	FMCDE_1V8	-
	I/O	44	22	Bank 64 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 228 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 64 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 228 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

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Table 32: FMC E connector cooling fan

XMOD Interface

JTAG access to the ... is provided through XMOD connector ....

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Table 5: JTAG interface signals.

Gigabit Ethernet Interface

USB3 Interface

SFP+ Interface

SSD Interface

DisplayPort Interface

DDR4 Memory Socket

CAN Interface

SD Card Interface

Describe SD Card interface shortly here if the module has one...

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Table x: SD Card interface signals and connections.

PLL Clock Programing Interface

4-Wire PWM FAN Connectors

SMA Coax Clock Input

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

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High-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

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Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

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The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.

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On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

8-Channel I²C Switches

All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

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Table 20: On-board peripherals' I²C-interfaces device slave addresses

Configuration EEPROMs

The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

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Table 21: On-board configuration EEPROMs overview

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEB0911 UltraRack board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Oscillators

The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

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Table 16: Reference clock signal oscillators

Programmable Clock Generator Si5338A

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

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Table : Programmable quad PLL clock generator inputs and outputs.

Programmable Clock Generator Si5345A

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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Table : Reference clock signals.

On-board LEDs

LED	Color	Connected to	Description and Notes
D1	Green
..	..	..	..

Table : On-board LEDs.

User Buttons

Configuration DIP-switches

Backup Battery Holder

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the board mainly depends on the design running on the FPGA.

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Battery Power Domain (BBRAM and RTC)
Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
Programmable Logic (PL)

Power Distribution Dependencies

There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power-On Sequence

The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

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Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

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Note
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 (MIO0)	PS_1.8V	1.8V	-
501 (MIO1)	PS_1.8V	1.8V	-
502 (DDR3)	1.35V	1.35V	-
12 HR	VCCIO_12	User	HR: 1.2V to 3.3V
13 HR	VCCIO_13	User	HR: 1.2V to 3.3V
33 HP	VCCIO_33	User	HP: 1.2V to 1.8V
34 HP	VCCIO_34	User	HP: 1.2V to 1.8V
35 HP	VCCIO_35	User	HP: 1.2V to 1.8V

Table : Module PL I/O bank voltages.

Board to Board Connectors

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	4 x 5 SoMs - LSHM B2B Connectors
	4 x 5 SoMs - LSHM B2B Connectors

Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Module Variant	FPGA / SoC	Operating Temperature	Temperature Range
TE0710-02-35-2CF	XC7A35T-2CSG324C	0°C to +70°C	Commercial
TE0715-04-30-3E	XC7Z030-3SBG485E	0°C to +85°C	Extended
TE0841-01-035-1I	XCKU035-1SFVA784I	–40°C to +85°C	Industrial
..	..	..	..

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage			V	-
Storage temperature			°C	-

...

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage
Operating temperature

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Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

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Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

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Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
-	01	Prototypes

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Figure : Module hardware revision number.

Document Change History

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Table : Document change history.

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

02 Sept 2017

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 63

New Version 64

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Boot Process

Signals, Interfaces and Pins

FMC Connectors

XMOD Interface

Gigabit Ethernet Interface

USB3 Interface

SFP+ Interface

SSD Interface

DisplayPort Interface

DDR4 Memory Socket

CAN Interface

SD Card Interface

PLL Clock Programing Interface

4-Wire PWM FAN Connectors

SMA Coax Clock Input

On-board Peripherals

System Controller CPLD

High-speed USB ULPI PHY

4-port USB3.0 Hub

Gigabit Ethernet PHY

8-Channel I²C Switches

Configuration EEPROMs

CAN FD Transceiver

eMMC Memory

Quad SPI Flash Memory

MAC Address EEPROM

Oscillators

Programmable Clock Generator Si5338A

Programmable Clock Generator Si5345A

Oscillators

On-board LEDs

User Buttons

Configuration DIP-switches

Backup Battery Holder

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Disclaimer