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The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins and singled ended PL pins:
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to reset the board if voltage failure occurs. A manual resetis also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND. Refer to documentation of the SC CPLD firmware for detailed information.
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| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D6 | red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, |
| D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
| D18 | green | USB3 Hub U4, pin 4 | LED output for downstream 1 port |
| D19 | green | USB3 Hub U4, pin 63 | LED output for downstream 3 port |
| D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status LED |
| D4 | green | SC CPLD U27, bank 2, pin AB18 | SFP+ interface status LED |
| D3 | red | SC CPLD U27, bank 2, pin AA16 | SFP+ interface status LED |
| D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED |
| D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 refer to the documentation section: LED |
| D14 | green | SC CPLD U27, bank 2, pin V12 | |
| D15 | green | SC CPLD U27, bank 2, pin W12 | |
| D1D16 | red | SC CPLD U27, bank 2, pin V13 |
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There are two switch buttons available to the user connected to the SC CPLD U27:
| Button |
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| Connected to |
|---|
| Notes |
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Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.
LED is on if all USB3 and USB2 ports are in the suspend state and is
off when one of the ports comes out of the suspend state.
| S1 | SC CPLD U27, bank 0, pin F13 | high active logic, connected to 3V3SB, functionality depends on the current firmware of the SC CPLD U27 |
| S2 |
| SC CPLD U27, bank |
| 0, pin G13 |
Table 54: On-board switch buttons
Configuration DIP-switches
There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
| DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes | |||||
|---|---|---|---|---|---|---|---|---|---|
| S3-1 | PUDC_B | Zynq MPSoC U1, pin AD15 | Positions ON: PUDC_B is Low OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position, means I/O's are 3-stated until configuration of the FPGA completes. | |||||
| S3-2 | JTAGENB | SC CPLD U27, bank 0, pin A16 | Positions | JTAG interface of the SC CPLD, accessible on XMOD header J35 | |||||
| S3-3 | SC_SW1 | AB17SFP+ interface status LED | D4 | green | SC CPLD U27, bank 20, pin AB18 | SFP+ interface status LED | E17 | set 2-bit code for boot mode selection | TEB0911 CPLD Firmware Documentation Section: Boot Mode |
| S3-4 | SC_SW2 | D3 | red | SC CPLD U27, bank 20, pin AA16 | SFP+ interface status LED | ||||
| D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED | ||||||
| D16 | |||||||||
| DIP-switch S4 | Signal Schematic Name | Connected to | Functionality | Notes | |||||
| S4-1 | U_SW1 | D13 | green | SC CPLD U27, bank 20, pin U12 | functionality depends on the current firmware of the SC CPLD U27 | D18 | user defined | - | |
| S4-2 | U_SW2 | D14 | green | SC CPLD U27, bank 20, pin V12D16 | D15 | ||||
| S4-3 | U_SW3green | SC CPLD U27, bank 20, pin W12C19 | |||||||
| S4-4 | U_SW4 | D1 | red | SC CPLD U27, bank 20, pin V13C18 |
Configuration DIP-switches
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Table 55: DIP-switch S3 and S4 functionality description
Power and Power-On Sequence
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Overview
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