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Anchor FMC A FMC A
FMC A
FMC A Interfaces:Scroll Landscape
| FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
|---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
| 46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
| I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
| JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
| MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
| Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
| Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
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Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
| DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes |
|---|---|---|---|---|
| S3-1 | PUDC_B | Zynq MPSoC U1, pin AD15 | Positions ON: PUDC_B is Low OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position, means I/O's are 3-stated until configuration of the FPGA completes. |
| S3-2 | JTAGENB | SC CPLD U27, bank 0, pin A16 | Positions | JTAG interface of the SC CPLD, accessible on XMOD header J35 |
| S3-3 | SC_SW1 | SC CPLD U27, bank 0, pin E17 | set 2-bit code for boot mode selection | TEB0911 CPLD Firmware Documentation Section: Boot Mode |
| S3-4 | SC_SW2 | SC CPLD U27, bank 0, pin D16 | ||
| DIP-switch S4 | Signal Schematic Name | Connected to | Functionality | Notes |
| S4-1 | U_SW1 | SC CPLD U27, bank 0, pin D18 | user defined | - |
| S4-2 | U_SW2 | SC CPLD U27, bank 0, pin D16 | ||
| S4-3 | U_SW3 | SC CPLD U27, bank 0, pin C19 | ||
| S4-4 | U_SW4 | SC CPLD U27, bank 0, pin C18 |
Table 55: DIP-switch S3 and S4 functionality description
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