Page History

...

Single 24V main power supply
2x USB3 A Connector (Superspeed Host Port (Highspeed at in USB2 mode))
Gigabit Ethernet RGMII PHY with RJ45 MegJack
Dual SFP+ Connector (2x1 Cage)
DDR4-SDRAM SODIMM socket (64bit bus width)
SSD (Solid State Disk) Connector
CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
1x DisplayPort
4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
6x FMC HPC Connectors
6x FMC Fans
3x Optional 4-wire PWM fan connectors
10 output programmable PLL clock generator Si5345A
Quad programmable PLL clock generator SI5338A
1x SMA coaxial connectors for reference clock signal input
MicroSD-Socket (bootable)
32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
System Controller CPLD Lattice MachXO2 7000 HC
2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
On-board DC-DC PowerSoCs and LDOs

...

Put your block diagram here...

Scroll Title

anchor	Figure_1
title	Figure 1: TEB0911-03 block diagram

...

Put top and bottom pics with labels of the real PCB here...

Scroll Title

anchor	Figure_2
title	Figure 2: TEB0911-03 main components

...

Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboardboard, section boot mode.

Signals, Interfaces and Pins

...

Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

Scroll Title

anchor	Figure_3
title	Figure 3: General overview of the FMC connectors

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	FMC Diagramm formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	5

...

Anchor

	FMC A
	FMC A

FMC A

FMC A Interfaces:scroll-landscape

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J10 (FMC A)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
	I/O	46	28	SC CPLD U27 Bank 1	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 128 GTH	-	4x MGT lanes
	Clock Input	-	1	Bank 128 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

...

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Connector Pin	FPGA Pin
J10 (FMC A)	0	128	GTH	B128_RX0_P B128_RX0_N B128_TX0_P B128_TX0_N	J10-C6 J10-C7 J10-C2 J10-C3	MGTHRXP0_128, T33 MGTHRXN0_128, T34 MGTHTXP0_128, T29 MGTHTXN0_128, T30
	1	128	GTH	B128_RX1_P B128_RX1_N B128_TX1_P B128_TX1_N	J10-A2 J10-A3 J10-A22 J10-A23	MGTHRXP1_128, P33 MGTHRXN1_128, P34 MGTHTXP1_128, R31 MGTHTXN1_128, R32
	2	128	GTH	B128_RX2_P B128_RX2_N B128_TX2_P B128_TX2_N	J10-A6 J10-A7 J10-A26 J10-A27	MGTHRXP2_128, N31 MGTHRXN2_128, N32 MGTHTXP2_128, P29 MGTHTXN2_128, P30
	3	128	GTH	B128_RX3_P B128_RX3_N B128_TX3_P B128_TX3_N	J10-A10 J10-A11 J10-A30 J10-A31	MGTHRXP3_128, M33 MGTHRXN3_128, M34 MGTHTXP3_128, M29 MGTHTXN3_128, M30

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J10

(FMC A)

B128_CLK0_P
B128_CLK0_N

128

J10-D4
J10-D5

MGTREFCLK0P_128, R27
MGTREFCLK0N_128, R28

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J10 (FMC A)	FMCA_3V3	J10-D36 J10-D38 J10-D40 J10-C39	DCDC U32, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin Y18 Signal: 'EN_A_3V3'
	3V3SB	J10-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V_FMC_AF	J10-C35 J10-C37	DCDC U51, max. cur.: 5A	-
	FMCAF_1V8	J10-H40 J10-G39 J10-F40 J10-E39	DCDC U39, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin W19 Signal: 'EN_AF_1V8'

...

FMC

MGT Lane

Bank

Type

Signal Schematic Name

FMC Connector Pin

FPGA Pin

J21

(FMC F)

0

129

GTH

B129_RX0_P
B129_RX0_N
B129_TX0_P
B129_TX0_N

J21-C6
J21-C7
J21-C2
J21-C3

MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

1

129

GTH

B129_RX1_P
B129_RX1_N
B129_TX1_P
B129_TX1_N

J21-A2
J21-A3
J21-A22
J21-A23

MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J21

(FMC F)

B129_CLK0_P
B129_CLK0_N

129

J21-D4
J21-D5

MGTREFCLK0P_129, L27
MGTREFCLK0N_129, L28

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J21 (FMC F)	FMCF_3V3	J21-D36 J21-D38 J21-D40 J21-C39	DCDC U42, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin Y10 Signal: 'EN_F_3V3'
	3V3SB	J21-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V_FMC_AF	J21-C35 J21-C37	DCDC U51, max. cur.: 5A	-
	FMCAF_1V8	J21-H40 J21-G39 J21-F40 J21-E39	DCDC U39, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin W19 Signal: 'EN_AF_1V8'

...

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Connector Pin	FPGA Pin
J4 (FMC B)	3	130	GTH	B130_RX3_P B130_RX3_N B130_TX3_P B130_TX3_N	J4-C6 J4-C7 J4-C2 J4-C3	MGTHRXP3_130, B33 MGTHRXN3_130, B34 MGTHTXP3_130, A31 MGTHTXN3_130, A32
	2	130	GTH	B130_RX2_P B130_RX2_N B130_TX2_P B130_TX2_N	J4-A2 J4-A3 J4-A22 J4-A23	MGTHRXP2_130, C31 MGTHRXN2_130, C32 MGTHTXP2_130, B29 MGTHTXN2_130, B30
	1	130	GTH	B130_RX1_P B130_RX1_N B130_TX1_P B130_TX1_N	J4-A6 J4-A7 J4-A26 J4-A27	MGTHRXP1_130, D33 MGTHRXN1_130, D34 MGTHTXP1_130, D29 MGTHTXN1_130, D30
	0	130	GTH	B130_RX0_P B130_RX0_N B130_TX0_P B130_TX0_N	J4-A10 J4-A11 J4-A30 J4-A31	MGTHRXP0_130, E31 MGTHRXN0_130, E32 MGTHTXP0_130, F29 MGTHTXN0_130, F30

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J4

(FMC B)

B130_CLK0_P
B130_CLK0_N

130

J4-D4
J4-D5

MGTREFCLK0P_130, G27
MGTREFCLK0N_130, G28

Supplied by attached module

B_CLK0_M2C_P
B_CLK0_M2C_N

48 HD

J4-H4
J4-H5

IO_L6P_HDGC_48, F17
IO_L6N_HDGC_48, F18

Supplied by attached module

B_CLK1_M2C_P
B_CLK1_M2C_N

48 HD

J4-G2
J4-G3

IO_L5P_HDGC_48, G18
IO_L5N_HDGC_48, G19

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J4 (FMC B)	FMCB_3V3	J4-D36 J4-D38 J4-D40 J4-C39	DCDC U33, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin G11 Signal: 'EN_B_3V3'
	3V3SB	J4-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J4-C35 J4-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J4-H40 J4-G39 J4-F40 J4-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin A3 Signal: 'EN_BC_1V8'

...

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Connector Pin	FPGA Pin
J8 (FMC C)	3	230	GTH	B230_RX3_P B230_RX3_N B230_TX3_P B230_TX3_N	J8-C6 J8-C7 J8-C2 J8-C3	MGTHRXP3_230, A4 MGTHRXN3_230, A3 MGTHTXP3_230, A8 MGTHTXN3_230, A7
	2	230	GTH	B230_RX2_P B230_RX2_N B230_TX2_P B230_TX2_N	J8-A2 J8-A3 J8-A22 J8-A23	MGTHRXP2_230, B2 MGTHRXN2_230, B1 MGTHTXP2_230, B6 MGTHTXN2_230, B5
	1	230	GTH	B230_RX1_P B230_RX1_N B230_TX1_P B230_TX1_N	J8-A6 J8-A7 J8-A26 J8-A27	MGTHRXP1_230, C4 MGTHRXN1_230, C3 MGTHTXP1_230, D6 MGTHTXN1_230, D5
	0	230	GTH	B230_RX0_P B230_RX0_N B230_TX0_P B230_TX0_N	J8-A10 J8-A11 J8-A30 J8-A31	MGTHRXP0_230, D2 MGTHRXN0_230, D1 MGTHTXP0_230, E4 MGTHTXN0_230, E3

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J8

(FMC C)

B230_CLK0_P
B230_CLK0_N

230

J8-D4
J8-D5

MGTREFCLK0P_230, C8
MGTREFCLK0N_230, C7

Supplied by attached module

C_CLK0_M2C_P
C_CLK0_M2C_N

50 HD

J8-H4
J8-H5

IO_L7P_HDGC_50, J12
IO_L7N_HDGC_50, H12

Supplied by attached module

C_CLK1_M2C_P
C_CLK1_M2C_N

50 HD

J8-G2
J8-G3

IO_L8P_HDGC_50, H13
IO_L8N_HDGC_50, G13

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J8 (FMC C)	FMCC_3V3	J8-D36 J8-D38 J8-D40 J8-C39	DCDC U34, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin E11 Signal: 'EN_C_3V3'
	3V3SB	J8-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J8-C35 J8-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J8-H40 J8-G39 J8-F40 J8-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin A3 Signal: 'EN_BC_1V8'

...

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Donnector Connector Pin	FPGA Pin
J7 (FMC D)	3	229	GTH	B229_RX3_P B229_RX3_N B229_TX3_P B229_TX3_N	J7-C6 J7-C7 J7-C2 J7-C3	MGTHRXP3_229, F2 MGTHRXN3_229, F1 MGTHTXP3_229, F6 MGTHTXN3_229, F5
	2	229	GTH	B229_RX2_P B229_RX2_N B229_TX2_P B229_TX2_N	J7-A2 J7-A3 J7-A22 J7-A23	MGTHRXP2_229, H2 MGTHRXN2_229, H1 MGTHTXP2_229, G4 MGTHTXN2_229, G3
	1	229	GTH	B229_RX1_P B229_RX1_N B229_TX1_P B229_TX1_N	J7-A6 J7-A7 J7-A26 J7-A27	MGTHRXP1_229, J4 MGTHRXN1_229, J3 MGTHTXP1_229, H6 MGTHTXN1_229, H5
	0	229	GTH	B229_RX0_P B229_RX0_N B229_TX0_P B229_TX0_N	J7-A10 J7-A11 J7-A30 J7-A31	MGTHRXP0_229, K2 MGTHRXN0_229, K1 MGTHTXP0_229, K6 MGTHTXN0_229, K5

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J7

(FMC D)

B229_CLK0_P
B229_CLK0_N

229

J7-D4
J7-D5

MGTREFCLK0P_229, G8
MGTREFCLK0N_229, G7

Supplied by attached module

D_CLK0_M2C_P
D_CLK0_M2C_N

65 HP

J7-H4
J7-H5

IO_L14P_T2L_N2_GC_65, AG5
IO_L14N_T2L_N3_GC_65, AG4

Supplied by attached module

D_CLK1_M2C_P
D_CLK1_M2C_N

65 HP

J7-G2
J7-G3

IO_L13P_T2L_N0_GC_QBC_65, AE5
IO_L13N_T2L_N1_GC_QBC_65, AF5

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J7 (FMC D)	FMCD_3V3	J7-D36 J7-D38 J7-D40 J7-C39	DCDC U35, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin F8 Signal: 'EN_D_3V3'
	3V3SB	J7-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J7-C35 J7-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J7-H40 J7-G39 J7-F40 J7-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin C5 Signal: 'EN_DE_1V8'

...

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Connector Pin	FPGA Pin
J6 (FMC E)	3	228	GTH	B228_RX3_P B228_RX3_N B228_TX3_P B228_TX3_N	J6-C6 J6-C7 J6-C2 J6-C3	MGTHRXP3_228, L4 MGTHRXN3_228, L3 MGTHTXP3_228, M6 MGTHTXN3_228, M5
	2	228	GTH	B228_RX2_P B228_RX2_N B228_TX2_P B228_TX2_N	J6-A2 J6-A3 J6-A22 J6-A23	MGTHRXP2_228, M2 MGTHRXN2_228, M1 MGTHTXP2_228, N4 MGTHTXN2_228, N3
	1	228	GTH	B228_RX1_P B228_RX1_N B228_TX1_P B228_TX1_N	J6-A6 J6-A7 J6-A26 J6-A27	MGTHRXP1_228, P2 MGTHRXN1_228, P1 MGTHTXP1_228, P6 MGTHTXN1_228, P5
	0	228	GTH	B228_RX0_P B228_RX0_N B228_TX0_P B228_TX0_N	J6-A10 J6-A11 J6-A30 J6-A31	MGTHRXP0_228, T2 MGTHRXN0_228, T1 MGTHTXP0_228, R4 MGTHTXN0_228, R3

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

FMC

Clock Signal Schematic Name

Bank

FMC Connector Pin

FPGA Pin

Notes

J6

(FMC E)

B228_CLK0_P
B228_CLK0_N

228

J6-D4
J6-D5

MGTREFCLK0P_228, L8
MGTREFCLK0N_228, L7

Supplied by attached module

E_CLK0_M2C_P
E_CLK0_M2C_N

64 HP

J6-H4
J6-H5

IO_L12P_T1U_N10_GC_64, AL8
IO_L12N_T1U_N11_GC_64, AL7

Supplied by attached module

E_CLK1_M2C_P
E_CLK1_M2C_N

64 HP

J6-G2
J6-G3

IO_L11P_T1U_N8_GC_64, AK8
IO_L11N_T1U_N9_GC_64, AK7

Supplied by attached module

...

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J6 (FMC E)	FMCE_3V3	J6-D36 J6-D38 J6-D40 J6-C39	DCDC U36, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin E8 Signal: 'EN_E_3V3'
	3V3SB	J6-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J6-C35 J6-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J6-H40 J6-G39 J6-F40 J6-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin C5 Signal: 'EN_DE_1V8'

...

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:

Scroll Title

anchor	Figure_4
title	Figure 4: XMOD header J24 and J35

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	XMOD header diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	1

...

Connector	Interface	Signal Schematic Name	XMOD Header Pin	Connected to	VCCIO	VCC
XMOD Header J24	JTAG	F_TCK	J24-4	Bank 503 PS Config, Pin R25	PS_1V8	3V3SB
		F_TDI	J24-10	Bank 503 PS Config, Pin U25
		F_TDO	J24-8	Bank 503 PS Config, Pin T25
		F_TMS	J24-12	Bank 503 PS Config, Pin R24
	GPIO/ UART	XMOD2_A	J24-3	SC CPLD U27, bank 5, Pin K7
		XMOD2_B	J24-7	SC CPLD U27, bank 5, Pin K6
		XMOD2_E	J24-9	SC CPLD U27, bank 5, Pin H7
		XMOD2_G	J24-11	SC CPLD U27, bank 5, Pin H6
XMOD Header J35	JTAG	C_TCK	J35-4	SC CPLD U27, bank 0, Pin A8	3V3SB
		C_TDI	J35-10	SC CPLD U27, bank 0, Pin C7
		C_TDO	J35-8	SC CPLD U27, bank 0, Pin A6
		C_TMS	J35-12	SC CPLD U27, bank 0, Pin C9
	GPIO/ UART	XMOD1_A	J35-3	SC CPLD U27, bank 0, Pin B19
		XMOD1_B	J35-9	SC CPLD U27, bank 0, Pin A17
		XMOD1_E	J35-7	SC CPLD U27, bank 0, Pin C17
		XMOD1_G	J35-11	SC CPLD U27, bank 0, Pin A18

...

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.

Scroll Title

anchor	Figure_5
title	Figure 5: Gigabit Ethernet interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	Gigabit Ethernet interface diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	1

...

On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.

Scroll Title

anchor	Figure_6
title	Figure 6: USB3 interface

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	USB3 interface diagram formatted
simpleViewer	false
width
diagramWidth	641
revision	1

...

IC	Interface	Signal Schematic Names	Connected to	NoteNotes
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_P B505_TX1_N B505_RX1_P B505_RX1_N PS GTR bank 505	Pins: PS_MGTRTXP1_505, Y29 PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31 PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P USB3_RXDN1_D_N USB3_TXDN1_D_P USB3_TXDN1_D_N USB3_RXDN2_D_P USB3_RXDN2_D_N USB3_TXDN2_D_P USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	USB2 Downstream LVDS pair	USB2_DN1_D_P USB2_DN1_D_N USB2_DN2_D_P USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	I²C	USBH_SDA USBH_SCL	USB3 hub U4 Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4-
	Control Lines	USBH_MODE0, USBH_MODE1 USBH_RST	SC CPLD U27, bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP USB0_NXT USB0_DIR USB0_CLK USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD U27, bank 4 Pin: M2	-

...

Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

Scroll Title

anchor	Figure_7
title	Figure 7: SFP+ interface

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	SFP interface diagram formatted
simpleViewer	false
width
diagramWidth	641
revision	1

...

-I/O Port Expander on
same I²C line as
SFP0-I²C-interface-
I/O Port Expander on
same I²C line as
SFP0-I²C-interface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P B129_TX3_N B129_RX3_P B129_RX3_N	GTH bank 129 Pins: MGTHTXP3_129, G31 MGTHTXN3_129, G32 MGTHRXP3_129, F33 MGTHRXN3_129, F34 BiDir	TX: Output RX: Input	Multi gigabit highspeed data lane-	-
	I²C	SFP0_SDA SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth	Low active
		SFP0_RS1		Output, low active	Reduced RX bandwidth	Low active
		SFP0_M-DEF0		Input, low active	Module present / not presentLow active
		SFP0_TX_FAULT		Input, high active	Fault / Normal Operation	High active
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input, high active	Loss of receiver signal	High active	-
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output, low active	SFP Enabled / Disabled	Low active	-
SFP+ J9B	MGT Lane	B129_TX2_P B129_TX2_N B129_RX2_P B129_RX2_N	GTH bank 129 Pins: MGTHTXP2_129, H29 MGTHTXN2_129, H30 MGTHRXP2_129, H33 MGTHRXN2_129, H34 BiDir	TX: Output RX: Input	Multi gigabit highspeed data lane	-
	I²C	SFP1_SDA SFP1_SCL	8-channel I²C-switch U37	BiDirBidir	2-wire Serial Interface	-	-
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth	Low active
		SFP1_RS1		Output, low active	Reduced RX bandwidthLow active
		SFP1_M-DEF0		Input, low active	Module present / not presentLow active
		SFP1_TX_FAULT		Input, high active	Fault / Normal Operation	High active
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input, high active	Loss of receiver signal	High active	-
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output. low active	SFP Enabled / DisabledLow active	-

Table 37: SFP+ signals and interfaces

...

On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.

Scroll Title

anchor	Figure_8
title	Figure 8: SSD interface

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	SSD interface diagram formatted
simpleViewer	false
width
diagramWidth	642
revision	1

...

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N PS GTR bank 505 Pins:	PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	TX: Output RX: Input -
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0-	Reference clock signal	-	-
	Control Lines	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	Output	LED, Output, High active-
			SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12Input	PCIe sleep state, Input, Low active
			SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	Input	PCIe reset input, Input, Low active-
			SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	Input	PCIe Link reactivation, Input, Low active-
			SSD1_CLKRQ	connect to GNDBiDir	PCIe Clock Request, Low active	-

Table 38: SSD signals and interfaces

...

The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

Scroll Title

anchor	Figure_9
title	Figure 9: DisplayPort interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	DisplayPort interface diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	2

...

-Input

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Notes
DisplayPort Connector J12	MGT Lane	B505_TX2_P B505_TX2_N B505_TX3_P B505_TX3_N PS GTR bank 505	Pins: PS_MGTRTXP2_505, W31 PS_MGTRTXN2_505, W32 PS_MGTRTXP3_505, V29 PS_MGTRTXN3_505, V30	Output	Multi gigabit highspeed data lane (only transmit pairs)	TX: Output RX: Input
	Auxiliary Line	DP_TX_AUX_P DP_TX_AUX_N	LVDS Line Driver/Receiver, U30-	Convert signal from single ended to LVDS Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX', SC CPLD U27, bank 2, pins AA14, AB12 -
	Control Lines	DP_TX_HPD	SC CPLD U27, bank 2, pin AA15		DisplayPort Hot Plug Detect	-
	Control Lines	DP_EN	LDO U29	-	3.3V Supply Voltage for DisplayPort-

Table 39: DisplayPort signals and interfaces

...

On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.

Scroll Title

anchor	Figure_10
title	Figure 10: DDR4 memory interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	DDR4 memory interface diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	642
revision	1

...

Connector	DDR4 SDRAM I/O Signal	Signal Schematic Name	Description	Connected to	Notes
DDR4 SO-DIMM Socket U13	Address inputs	DDR4-A0 ... DDR4-A16 -	PS DDR Bank 504	-
	Bank address inputs	DDR4-BA0 / DDR4-BA1 -		-
	Bank group inputs	DDR4-BG0 / DDR4-BG1 -		-
	Differential clocks	DDR4-CLK0_P DDR4-CLK0_N DDR4-CLK1_P DDR4-CLK1_N		2 x DDR4 clock-
	Data input/output	DQ0 ... DQ63		-	-
	Check bit input/output	CB0 ... CB7		-	-
	Data strobe (differential)	DDR4-DQS0_P DDR4-DQS0_N ... DDR4-DQS8_P DDR4-DQS8_N -		-
	Data mask and data bus inversion	DDR4-DM0 ... DDR4-DM8		-	-
	Serial address inputs	DDR4-SA0 ... DDR4-SA2		address range configuration on I²C bus -
	Control Signals	DDR4-CS_N0 / DDR4-CS_N1		chip selest signal-
		DDR4-ODT0 / DDR4-ODT1		On-die termination enable-
		DDR4-RESET		nRESET-
		DDR4-PAR		Command and address parity input	-
		DDR4-CKE0 / DDR4-CKE1		Clock enable	-
		DDR4-ALERT		CRC error flag	-
		DDR4-ACT		Activation command input-
		DDR4-EVENT		Temperature event	-
	I²C	DDR4-SCL DDR4-SDA -	8-channel I²C switch U37	-

Table 40: DDR4 64-bit memory interface signals and pins

...

The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:

Scroll Title

anchor	Figure_11
title	Figure 11: CAN interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	CAN interface diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	2

...

Connector	Signal Schematic Name	Connected to	Notes
D-SUB 9-pin male connector J3	CAN_H , pin 7	CAN Transceiver U48, pin 7	-
D-SUB 9-pin male connector J3	CAN_L , pin 2	CAN Transceiver U48, pin 6	-
6-pin male header J15	CAN_H , pin 4	CAN Transceiver U48, pin 7	-
6-pin male header J15	CAN_L , pin 3	CAN Transceiver U48, pin 6	-
CAN Transceiver	Signal Schematic Name	Connected to	Notes
TCAN337 U48	CAN_TX	SC CPLD U27, bank 0, pin C16	3.3V VCCIO
	CAN_RX	SC CPLD U27, bank 0, pin B15	3.3V VCCIO
	CAN_S	SC CPLD U27, bank 0, pin C15	3.3V VCCIO
	CAN_FAULT	SC CPLD U27, bank 0, pin D15	3.3V VCCIO

...

The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

Scroll Title

anchor	Figure_12
title	Figure 12: SD Card interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	SD Card interface diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	1

...

Connector	Signal Schematic Name	Connected to	Notes
SD Card Socket J11	SD_DAT0 , J11-7	PS bank 501 Pins: MIO46 ... MIO51	-
	SD_DAT1 , J11		-8	-
	SD_DAT2 , J11-9		-
	SD_DAT3 , J11-1		-
	SD_CMD , J11-2		-
	SD_CK , J11-5		-
	SD_CD , J11-10	SC CPLD U27, bank 2, pin T11	Card Detect
	SD_WP , J11-11	SC CPLD U27, bank 2, pin T10	Write Protect

...

The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:

Scroll Title

anchor	Figure_13
title	Figure 13: 4-wire PWM FAN connectors

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	4-Wire PWM FAN connectors diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	2

Connector	Signal Schematic Name	Connected to	Notes
Fan Connector J2	F1PWM	SC CPLD U27, bank 0, pin E10	-
	F1SENSE	SC CPLD U27, bank 0, pin D11	-
	F1_EN	SC CPLD U27, bank 0, pin C8	Controls 12V Load Switch
Fan Connector J23	F2PWM	SC CPLD U27, bank 0, pin D9	-
	F2SENSE	SC CPLD U27, bank 0, pin G12	-
	F2_EN	SC CPLD U27, bank 0, pin B4	Controls 12V Load Switch
Fan Connector J33	F3PWM	SC CPLD U27, bank 0, pin B13	-
	F3SENSE	SC CPLD U27, bank 0, pin A13	-
	F3_EN	SC CPLD U27, bank 0, pin A12	Controls 12V Load Switch

...

With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.

Scroll Title

anchor	Figure_14
title	Figure 14: PLL clock interface

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	PLL clock interfaces diagram formatted
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	1

...

Connector

Signal Schematic Name

Connected to

Notes

Pin Header

J22

PLL_SCL

clock generator U17, pin 16

PS_1V8 VCCIO

PLL_SDA

clock generator U17, pin 18

SMA Coax

J25

CLK_PLL_IN

clock generator U17, pin 1

-

...

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins and singled ended PL pins:

Scroll Title

anchor	Figure_15
title	Figure 15: I/O's connecting Zynq MPSoC and SC CPLD

draw.io Diagram

border	truefalse
viewerToolbar	true

fitWindow	false
diagramName	SC CPLD connections to Zynq MPSoC
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	1

For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.

...

MIO	Signal Schematic Name	Notes
38	I2C_SCL	3.3V reference voltage
39	I2C_SDA	3.3V reference voltage

Table 46: MIO-pin assignment of the module's I²C interface

...

I²C Slave Devices connected to MPSoC I²C Interface	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
8-channel I²C switch U13	-	0x76	I2C_SDA / I2C_SCL
8-channel I²C switch U37	-	0x77	I2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U13	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
FMC Connector J7 (FMC D)	2	0x50	FMCD_SDA / FMCD_SCL
FMC Connector J6 (FMC E)	3	0x50	FMCE_SDA / FMCE_SCL
FMC Connector J4 (FMC B)	4	0x50	FMCB_SDA / FMCB_SCL
FMC Connector J8 (FMC C)	5	0x50	FMCC_SDA / FMCC_SCL
PLL clock generator U17 Si5345A	6	0x69	PLL_SDA / PLL_SCL
I²C Slave Devices connected to 8-channel I²C Switch U37	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
FMC Connector J10 (FMC A)	1	0x50	FMCA_SDA / FMCA_SCL
FMC Connector J21 (FMC F)	2	0x50	FMCF_SDA / FMCF_SCL
SFP+ Connector J9A	3	0x50 / 0x51	SFP0_SDA / SFP0_SCL
8-bit I²C IO Expander U86 (SPF+ connector control signals)	3	0x27	SFP0_SDA / SFP0_SCL
SFP+ Connector J9B	4	0x50 / 0x51	SFP1_SDA / SFP1_SCL
PLL clock generator U12 Si5338A	5	0x70	MEM_SDA / MEM_SCL
Configuration EEPROM U83	5	0x51	MEM_SDA / MEM_SCL
Configuration EEPROM U45	5	0x52	MEM_SDA / MEM_SCL
Configuration EEPROM U60	5	0x53	MEM_SDA / MEM_SCL
Configuration EEPROM U57	5	0x57	MEM_SDA / MEM_SCL
SC CPLD U27	5	user configurable	MEM_SDA / MEM_SCL
DDR4 SODIMM I²C interface	6	module dependent	DDR4-SDA / DDR4-SCL
USB3 Hub U4	7	0x60	USBH_SDA / USBH_SCL
USB3 Hub configuration EEPROM U5	7	0x51	USBH_SDA / USBH_SCL

Table 46: On-board peripherals' I²C-interfaces device slave addresses

...

The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

EEPROM Modell	Schematic Designator	Memory Density	Purpose
24LC128-I/ST	U57	128 Kbit	user
24AA025E48T-I/OT	U60	2 Kbit	user
24AA025E48T-I/OT	U45	2 Kbit	user
24AA025E48T-I/OT	U83	2 Kbit	user
24LC128-I/ST	U5	128 Kbit	USB3 Hub U4 configuration memory

...

Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.

MIO	Signal Schematic Name	Flash U24 Pin	MIO	Signal Schematic Name	Flash U25 Pin	MIO	Signal Schematic Name	Flash U26 Pin
0	SPI Flash CLK MIO0	B2	7SPI	Flash CS MIO7	C2	13	MMC-D0	H3
1SPI	Flash IO1 MIO1	D2	8SPI	Flash IO0 MIO8	D3	14	MMC-D1	H4
2SPI	Flash IO2 MIO2	C4	9SPI	Flash IO1 MIO9	D2	15	MMC-D2	H5
3SPI Flash IO3	MIO3	D4	10SPI	Flash IO2 MIO10	C4	16	MMC-D3	J2
4SPI	Flash IO0 MIO4	D3	11	SPI Flash IO3 MIO11	D4	17	MMC-D4	J3
5SPI	Flash CS MIO5	C2	12SPI	Flash CLK MIO12	B2	18	MMC-D5	J4
						19	MMC-D6	J5
						20	MMC-D7	J6
						21	MMC-CMD	W5
						22	MMC-CLKR	W6
						23	MMC MM_ RST	U5

Table 49: PS MIO pin assignment of the Flash memory ICs

...

The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Clock Source	Signal Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U22	PS_CLK	33.333333 MHz	Zynq MPSoC PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U16	USB_CLK	52.000000 MHz	USB2 transceiver PHY U15, pin 26
Kyocera CX3225SB26000, Y3	-	26.000 MHz	4-port USB3 Hub U4, pin 68/69
Kyocera CX3225SB26000, Y2	XAXB_P XAXB_N	54.000 MHz	PLL clock generator U17, pin 8/9
SiTime SiT8008BI oscillator, U21	ETH_CLKIN	25.000000 MHz	Gigabit Ethernet PHY U20, pin 34
SiTime SiT8008AI oscillator, U87 optional, not equipped	CLK_SC	25.000000 MHz	System Controller CPLD U27, bank 2, pin AA9
SiTime SiT8008BI oscillator, U18	IN0_P	25.000000 MHz	PLL clock generator U17, pin 63
SiTime SiT8008AI oscillator, U85	-	25.000000 MHz	PLL clock generator U12, pin 3
DSC1123 oscillator, U92 optional, not equipped	B505_CLK3_P B505_CLK3_N	100.0000 MHz	PS GTR Bank 505 Lane 3, dedicated for DisplayPort, Pin U31, U32

...

There is a Si5338A U12, Silicon Labs I²C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.

Si5338A Pin	Signal Schematic Name / Description	Connected Toto	Clock Direction	Note
IN1	CLK8_N	U17, pin 54	Input	Differential reference clock input from PLL clock generator U17
IN2	CLK8_P	U17, pin 53	Input
IN3Reference input clock	-	U85, pin 3	Input	25.000000 MHz oscillator, Si8008AI
IN4	-	GND	Input	LSB (pin 'IN4') of the default I²C-adress 0x70 not set
IN5	-	Not connected	Input	Not used
IN6	-	GND	Input	Not used
CLK0A	SSD_RCLK_P	U2, pin 55	Output	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface
CLK0B	SSD_RCLK_N	U2, pin 53	Output	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface
CLK1A	B505_CLK2_N	U1, pin U27	Output	PS GTR Bank 505 Lane 2, dedicated for DisplayPort,
CLK1B	B505_CLK2_P	U1, pin U28	Output	PS GTR Bank 505 Lane 2, dedicated for DisplayPort,
CLK2A	B505_CLK1_N	U1, pin W27	Output	PS GTR Bank 505 Lane 1, dedicated for USB3 interface
CLK2B	B505_CLK1_P	U1, pin W28	Output	PS GTR Bank 505 Lane 1, dedicated for USB3 interface
CLK3A	B505_CLK0_P	U1, pin AA27	Output	PS GTR Bank 505 Lane 0, dedicated for SSD interface
CLK3B	B505_CLK0_N	U1, pin AA28	Output	PS GTR Bank 505 Lane 0, dedicated for SSD interface

Table 51: Programmable quad PLL clock generator inputs and outputs

...

Following table shows on-board Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Si5345A Pin	Signal Schematic Name / Description	Connected Toto	Clock Direction	Note
IN0	IN0_P	not connected	Input	Not used
IN0	IN0_N	GND	Input	Not used
IN1	IN1_P	SMA Coax J25, pin 1	Input	external reference clock input
IN1	IN1_N	GND	Input	external reference clock input
IN2	-	not connected	Input	not used
IN2	-	not connected	Input	not used
IN3	-	not connected	Input	not used
IN3	-	not connected	Input	not used
OUT0	CLK0_P	not connected	Output	not used
OUT0	CLK0_N	not connected	Output	not used
OUT1	CLK1_P	U1, pin E8	Output	GTH bank 229 reference clock input
OUT1	CLK1_N	U1, pin E7	Output	GTH bank 229 reference clock input
OUT2	CLK2_P	U1, pin B10	Output	GTH bank 230 reference clock input
OUT2	CLK2_N	U1, pin B9	Output	GTH bank 230 reference clock input
OUT3	CLK3_P	U1, pin J8	Output	GTH bank 228 reference clock input
OUT3	CLK3_N	U1, pin J7	Output	GTH bank 228 reference clock input
OUT4	CLK4_P	U1, pin N27	Output	GTH bank 128 reference clock input
OUT4	CLK4_N	U1, pin N28	Output	GTH bank 128 reference clock input
OUT5	CLK5_P	U1, pin J27	Output	GTH bank 129 reference clock input
OUT5	CLK5_N	U1, pin J28	Output	GTH bank 129 reference clock input
OUT6	CLK6_P	U1, pin E27	Output	GTH bank 130 reference clock input
OUT6	CLK6_N	U1, pin E28	Output	GTH bank 130 reference clock input
OUT7	CLK7_P	U27, pin E1	Output	Clock signal input to SC CPLD, bank 5
OUT7	CLK7_N	not connected	Output	Clock signal input to SC CPLD, bank 5
OUT8	CLK8_P	U12, pin 2	Output	Differential reference clock input to PLL clock generator U12
OUT8	CLK8_N	U12, pin 1	Output
OUT9	-	not connected	Output	not used
OUT9	-	not connected	Output	not used
XA/XB	XAXB_P	54.000 MHz quartz oscillator Y1	Input	Differential quartz oscillator clock input
XA/XB	XAXB_N	54.000 MHz quartz oscillator Y1	Input	Differential quartz oscillator clock input

Table 52: Programmable 10-output PLL clock generator inputs and outputs

...

DIP-switch S3	Signal Schematic Name	Connected to	Functionality	Notes
S3-1	PUDC_B	Zynq MPSoC U1, pin AD15	Positions ON: PUDC_B is Low OFF: PUDC_B is HIGH	Internal pull-up resistors during configuration are enabled at ON-position, means I/O's are 3-stated until configuration of the FPGA completes.
S3-2	JTAGENB	SC CPLD U27, bank 0, pin A16	Positions ON: SC CPLD's JTAG enabled OFF: SC CPLD's JTAG disabled	JTAG interface of the SC CPLD, accessible on XMOD header J35
S3-3	SC_SW1	SC CPLD U27, bank 0, pin E17	set 2-bit code for boot mode selection	TEB0911 CPLD Firmware Documentation Section: Boot Mode
S3-4	SC_SW2	SC CPLD U27, bank 0, pin D16	set 2-bit code for boot mode selection	TEB0911 CPLD Firmware Documentation Section: Boot Mode
DIP-switch S4	Signal Schematic Name	Connected to	Functionality	Notes
S4-1	U_SW1	SC CPLD U27, bank 0, pin D18	user defined-	For functionalities of these switches in the current CPLD firmware, refer to the TEB0911 CPLD Firmware Documentation.
S4-2	U_SW2	SC CPLD U27, bank 0, pin D16
S4-3	U_SW3	SC CPLD U27, bank 0, pin C19
S4-4	U_SW4	SC CPLD U27, bank 0, pin C18

...

Power Input	Typical Current
24V VIN	TBD*

Table 56: Typical power consumption, *to Be Determined soon with reference design setup.

Power supply with minimum current capability of ?? A 2A for system startup is recommended. If using all FMC connectors with FPGA Mezzanine Cards, a higher current availability of up to 4A is recommended.

The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

...

There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Scroll Title

anchor	Figure_16
title	Figure 16: Power distribution diagram

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	Zynq MPSoC CPLD connections
simpleViewer	false
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	11

Power distribution to the MPSoC PS and PL units:

Scroll Title

anchor	Figure_17
title	Figure 17: Power distribution diagram continued

draw.io Diagram

border	false
viewerToolbar	true

fitWindow	false
diagramName	Power distribution diagram continued
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	641
revision	23

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power-On Sequence

Info
Note: The DC-DC converter U91 LTM4630EY has an integrated temperature diode for device temperature monitoring. The analog signal 'TEMP_CORE_DC' on pin J6 of the converter is routed to the dedicated differential analog interface (XADC) of the Zynq MPSoC, pin U18 (V_P), pin V17 (V_N) is connected to analog GND.

Power-On Sequence

The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

...

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Scroll Title

anchor	Figure_18
title	Figure 18: Power-On sequence diagram

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	Power-on sequence diagram
simpleViewer	false
width
diagramWidth	641
revision	1

...

2

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Peripheral Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J12	DP_TX_PWR	3.3V	Out	Pin 20	Display-Port Connector
J9A	SFP_SSD

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins

Direction

NotesVIN1, 3, 52, 4, 6, 8InputMain supply voltage from the carrier board.

3.3V

-

Out

10, 12, 91OutputModule on-board 3.3V voltage supply. (would be good to add max. current allowed here if possible)B64_VCO9, 11-InputHR (High Range) bank voltage supply from the carrier board.

VBAT_IN

79-InputRTC battery supply voltage from the carrier board................

Table : Module power rails

Bank Voltages

...

Bank

...

Voltage

...

Voltage Range

...

Pin T15, T16	SFP+ 2x1 Connector
J9B	SFP+ 2x1 Connector	SFP_SSD	3.3V	Out	Pin L15, L16
J13A	VBUS1	5.0V	Out	Pin U1	USB3 Ports
J13B	VBUS2	5.0V	Out	Pin U10	USB3 Ports
J11	-	3.3V	Out	Pin 4	MicroSD Card Socket
B1	PSBATT	3.0V	In	Pin +	Battery Holder CR1220
U2	SSD1_3V3_1	3.3V	Out	Pin 2, 4	SSD PCIe connector
	SSD1_3V3_2	3.3V	Out	Pin 70, 72, 74
	SSD1_3V3_3	3.3V	Out	Pin 12, 14, 16, 18
U3	DDR_1V2	1.2V	Out	Pin 111, 112, 117, 118, 123, 124, 129, 130, 135, 136, 141, 142, 147, 148, 153, 154, 159, 160, 163	DDR4 SO-DIMM socket
U3	VPP_SPD	2.5V	Out	Pin 255, 257, 259	DDR4 SO-DIMM socket

Table 57: Power pin description of Peripherals' Connector

XMOD / JTAG Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J24	3V3SB	3.3V	Out	Pin 5	Zynq MPSoC JTAG
J24	PS_1V8	1.8V	Out	Pin 6	Zynq MPSoC JTAG
J35	3V3SB	3.3V	Out	Pin 5, 6	SC CPLD JTAG

Table 58: Power pin description of XMOD/JTAG Connector

Main Power	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J1	PWR_IN_24V	24V	In	Pin 2, 4	24V Power Jack

Table 59: Power pin description of main power supply connector

FMC Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J10	12V_FMC_AF	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCA_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCAF_1V8	1.8V	Out	Pin E39, G39, H40, F40	-
J21	12V_FMC_AF	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCF_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCAF_1V8	1.8V	Out	Pin E39, G39, H40, F40	-
J4	12V	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCB_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCBC_1V8	1.8V	Out	Pin E39, G39, H40, F40	-
J8	12V	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCC_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCBC_1V8	1.8V	Out	Pin E39, G39, H40, F40	-
J7	12V	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCD_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCDE_1V8	1.8V	Out	Pin E39, G39, H40, F40	-
J6	12V	12.0V	Out	Pin C35, C37	-
	3V3VSB	3.3V	Out	Pin D32	-
	FMCE_3V3	3.3V	Out	Pin D36, D38, D40, C39	-
	FMCDE_1V8	1.8V	Out	Pin E39, G39, H40, F40	-

Table 60: Power pin description of FMC connectors

FAN Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J2	-	12.0V	Out	Pin 2	headers for optionals cooling FANs
J23	-	12.0V	Out	Pin 2
J33	-	12.0V	Out	Pin 2

Table 61: Power pin description of FAN connectors

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 (PS MIO)	PS_1V8	1.8V	all bank voltages fixed
501 (PS MIO)	3.3V	3.3V
502 (PS MIO)	PS_1V8	1.8V
503 (PS Config)	PS_1V8	1.8V
504 (PS DDR)	DDR_1V2	1.2V
64 HP	FMCDE_1V8	1.8V
65 HP	FMCDE_1V8	1.8V
66 HP	FMCDE_1V8	1.8V
67 HP	FMCBC_1V8	1.8V
44 HD	FMCAF_1V8	1.8V
47 HD	FMCBC_1V8	1.8V
48 HD	FMCBC_1V8	1.8V
49 HD	FMCBC_1V8	1.8V
50 HD	FMCBC_1V8	1.8V

Table 62: Zynq MPSoC PS/PL VCCO bank voltages

Variants Currently In Production

Trenz shop TEB9011 overview page
English page	German page

Table : Module PL I/O bank voltages

Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

...

Operating Temperature

...

Technical Specifications

Absolute Maximum Ratings

...

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage
Operating temperature

Table : Module recommended operating conditions

...

Include Page

	IN:Legal Notices
	IN:Legal Notices

02 Sept 2017

NLVREF066

Trenz Electronic Documentation

Versions Compared

Old Version 122

New Version 123

Key

Signals, Interfaces and Pins

Power-On Sequence

Power-On Sequence

Power Rails

Bank Voltages

Bank Voltages

Variants Currently In Production

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions