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Scroll Title
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titleFigure 1: TEB0911-03 block diagram


Main Components

Put top and bottom pics with labels of the real PCB here...

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titleFigure 2: TEB0911-03 main components

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TEB0911-03 main components

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  1. SFP+ 2x1 cage with integrated LED light pipes, J9
  2. DisplayPort connector, J12
  3. USB3 A 2x , RJ45 1x (stacked), J13
  4. FMC connector (FMC B), J4
  5. FMC B cooling fan, M2
  6. FMC connector (FMC C), J8
  7. FMC C cooling fan, M3
  8. FMC connector (FMC D), J7
  9. FMC D cooling fan, M4
  10. FMC connector (FMC E), J6
  11. FMC E cooling fan, M5
  12. I²C programming header of on-board PLL clock generator U17, J22
  13. 4-Wire PWM fan connector, J23
  14. Main Power Jack 24V, J1
  15. CAN bus D-SUB 9-pin male connector, J3
  16. CAN bus 6-pin header male, J15
  17. XMOD JTAG header for access to System Controller CPLD, J35
  18. XMOD JTAG header for access to Zynq MPSoC, J24

  1. FMC B cooling fan, M3
  2. MicroSD Card socket (on bottom side), J16
  3. DisplayPort connector, J13
  4. USB3.0 A 2x , RJ45 1x (stacked), J7
  5. SFP+ 2x1 cage, J14
  6. PCIe x16 connector (one PCIe lane connected), J11
  7. FMC HPC connector, J5
  8. FMC-Fan connector 5V, J19
  9. USB3.0 connector, J8
  10. PC-BEEPER 4-pin header, J23
  11. SMA coaxial connector (SI5338A clock output), J32
  12. SMA coaxial connector (clock input to MPSoC module), J33
  13. MMC Card socket, J27
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  18. CAN bus 6-pin header, J29
  19. CAN bus 10-pin connector, J24
  20. ARM JTAG  20-pin connector, J30
  21. ATX-24 power supply connector, J20
  22. 4-Wire PWM fan connector, J35
  23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
  24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
  25. Power Jack 2.1mm 12V, J25
  26. 4-bit DIP-switch, S5
  27. Power Button, S1
  28. Samtec FireFly connector  for reverse loopback, J21/J22
  29. Samtec FireFly connector (4 GT lanes bidirectional), J6/J15
  30. SATA header, J31
  31. 4-Wire PWM fan connector, J26
  32. I²C interface of programmable on-module PLL (10-pin header), J17
  33. Reset Button, S2
  34. INTEL HDA 9-pin header, J9
  35. Intel front panel (PWR-/RST-Button, HD-/PWR-LED) 9-pin header, J10
  36. Samtec FireFly connector J6/J15 I²C interface (3-pin header), J34
  37. 4-bit DIP-switch, S4
  38. PMOD connector, P3
  39. PMOD connector, P1
  40. Battery Holder CR1220, B1

Initial Delivery State

Storage device name

Content

Notes

User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)EmptyNot programmed
USB3 HUB Configuration EEPROM (Microchip 24LC128-I/ST)EmptyNot programmed
Si5338A programmable PLL NVM OTPEmptyNot programmed
Si5345A programmable PLL NVM OTPEmptyNot programmed

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LED ColorConnected toDescription and Notes
D6redZynq MPSoC U1, pin W21

Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.

D17greenUSB3 Hub U4, pin 25

LED is on if all USB3 and USB2 ports are in the suspend state and is
off when one of the ports comes out of the suspend state.

D18greenUSB3 Hub U4, pin 4LED output for downstream 1 port.
D19greenUSB3 Hub U4, pin 63LED output for downstream 3 port.
D2redSC CPLD U27, bank 2, pin AB17

SFP+ interface status.

The LEDs are fitted on-board under the SFP+ connector cage.
The light of the LEDs are conducted to the front of the connector
through integrated LED light pipes.

D4greenSC CPLD U27, bank 2, pin AB18SFP+ interface status LED
D3redSC CPLD U27, bank 2, pin AA16SFP+ interface status LED
D5greenSC CPLD U27, bank 2, pin AB15SFP+ interface status LED
D13greenSC CPLD U27, bank 2, pin U12

functionality depends on the current firmware of the SC CPLD U27

refer to the documentation

section: LED

D14greenSC CPLD U27, bank 2, pin V12
D15greenSC CPLD U27, bank 2, pin W12
D16redSC CPLD U27, bank 2, pin V13

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Scroll Title
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titleFigure 17: Power distribution diagram continued

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Warning

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To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Info

Note: The DC-DC converter U91 LTM4630EY has an integrated temperature diode for device temperature monitoring. The analog signal 'TEMP_CORE_DC' on pin J6 of the converter is routed to the dedicated differential analog interface (XADC) of the Zynq MPSoC, pin U18 (V_P), pin V17 (V_N) is connected to analog GND.

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power-On Sequence

The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

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Table 57: Power pin description of Peripheralsperipherals' Connectorconnectors


XMOD / JTAG DesignatorVCC / VCCIO Schematic NameVoltageDirectionPinsNotes
J24

3V3SB

3.3VOutPin 5Zynq MPSoC JTAG

PS_1V81.8VOutPin 6
J353V3SB3.3VOutPin 5, 6SC CPLD JTAG

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ParameterMinMaxUnitsReference DocumentNotes
VIN supply voltage2225VSchematic REV0324V nominal
VBATT2.25.5VTPS780180300 data sheetsupplied by 3.0V CR1220 battery
PL I/O input voltage (HP / HD bank)-0.2VCCO + 0.2VXilinx DS925 data sheetPL bank VCCO voltages are fixed at 1.8V
PS I/O input voltage-0.2VCCO + 0.2VXilinx DS925 data sheetsee section 'bank voltages' for PS bank VCCO
SC CPLD U27 I/O input voltage-0.33.6VLattice MachXO2 familiy data sheet-
SC CPLD U27 differential I/O input voltage02.605VLattice MachXO2 familiy data sheet-PLL clock generator input-0.23.0VSi5345/44/42 Rev D Data Sheet-
Operating temperature060°CF455B / Xilinx DS925 data sheet-

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The TEB0911 board is capable to be operated at an operational temperatur range of 0 °C ... 85 °C without FMC cooling fans M1 ... M6 and NGFF M.2 PCIe socket U2, which limit the temperatur range.

Physical Dimensions

  • Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... mm.

  • PCB thickness: ... mm.

  • Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

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Include Page
IN:Legal Notices
IN:Legal Notices

  1. FMC connector (FMC C), J8
  2. FMC B cooling fan, M3