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Table 1Figure 2: TEM0002-01 main components.

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Connections and Interfaces or B2B Pin's which are accessible by User
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I/Os

I/O signals provided on the Rasperry Pi compatible header are connected to the SoCs I/O bank and B2B connector: bank 2 of the Microsemi SoC.

Table x: General overview of PL I/O Table 2:General overview of I/O signals connected to the B2B connectorsSoC.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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PMODs

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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• MGT_RX0_P
• MGT_RX0_N
• MGT_TX0_P
• MGT_TX0_N

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• JM3-8
• JM3-10
• JM3-7
• JM3-9

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• MGTHRXP0_225, Y2
• MGTHRXN0_225, Y1
• MGTHTXP0_225, AA4
• MGTHTXN0_225, AA3

<!--
TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
  -->

PMODs

The module provides four 2x6 female pin header. Two of the headers are arranged to use as double PMOD. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.

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JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

SD Card Interface

The SD Card interface is connected to Bank 2 of the SoC

Table x6: SD Card interface signals and connections.

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