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Table of Contents

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/<name> for the current online version of this manual and other available documentation.


The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...

Key Features

List key features here, like FPGA type, amount and type of RAM, type of flash, etc.

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Put your block diagram here...

Figure 1: TE0xxx-xx block diagram.

Main Components

Put top and bottom pics with labels of the real PCB here...

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

Storage device name

Content

Notes

..

..

..
OTP Flash areaEmptyNot programmed.

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

MODE Signal State

Boot Mode

High or open

SD Card

Low or ground

QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

BankTypeB2B ConnectorI/O Signal CountBank VoltageNotes






64HRJM18 I/Os3.3VOn-module power supply.
66HPJM316 I/Os, 8 LVDS pairsB66_VCCOSupplied by the carrier board.

Table x: General overview of PL I/O signals connected to the B2B connectors.


All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

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MGT Lanes

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
0225GTH
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • MGTHRXP0_225, Y2
  • MGTHRXN0_225, Y1
  • MGTHTXP0_225, AA4
  • MGTHTXN0_225, AA3
1225GTH
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • MGTHRXP1_225, V2
  • MGTHRXN1_225, V1
  • MGTHTXP1_225, W4
  • MGTHTXN1_225, W3
............
4224GTH
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • JM1-12
  • JM1-10
  • JM1-6
  • JM1-4
  • MGTHRXP0_224, AH2
  • MGTHRXN0_224, AH1
  • MGTHTXP0_224, AG4
  • MGTHTXN0_224, AG3
5224GTH
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • JM1-24
  • JM1-22
  • JM1-18
  • JM1-16
  • MGTHRXP1_224, AF2
  • MGTHRXN1_224, AF1
  • MGTHTXP1_224, AF6
  • MGTHTXN1_224, AF5
............

Table x: MGT lanes.


Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
MGT_CLK0_P225B2B, JM3-33MGTREFCLK0P_225, Y6Supplied by the carrier board.
MGT_CLK0_N225B2B, JM3-31MGTREFCLK0N_225, Y5Supplied by the carrier board.
MGT_CLK1_P225U2, CLK1BMGTREFCLK1P_225, V6On-board Si5338A.
MGT_CLK1_N225U2, CLK1AMGTREFCLK1N_225, V5On-board Si5338A.
MGT_CLK2_P224B2B, JM3-34MGTREFCLK2P_224, AD6Supplied by the carrier board.
MGT_CLK2_N224B2B, JM3-32MGTREFCLK2N_224, AD5Supplied by the carrier board.
MGT_CLK3_P224U2, CLK2BMGTREFCLK3P_224, AB6On-board Si5338A.
MGT_CLK3_N224U2, CLK2BMGTREFCLK3N_224, AB5On-board Si5338A.

Table x: MGT reference clock sources.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

JTAG Signal

B2B Connector Pin

TCKJMx-xx
TDIJMx-xx
TDOJMx-xx
TMSJMx-xx

Table 5: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionB2B Connector PinDefault Configuration
PGOODOutputPower GoodJ1-148Active high when all on-module power supplies are working properly.
JTAGENInputJTAG SelectJ2-131Low for normal operation.
..........

Table x: System Controller CPLD I/O pins.


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Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

FPGA / SoC PinConnected ToSignal NameNotes
MIO0J10-9Card detect switch
MIO10J10-7DAT0
MIO11J10-3CMD
MIO12J10-5CLK
MIO13J10-8DAT1
MIO14J10-1DAT3
MIO15J10-2CD/DAT3

Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

PHY PinPSPLB2BNotes





Table x: ...

USB Interface

USB PHY is provided with ...

PHY PinPinB2B NameNotes




Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

I2C DeviceI2C AddressNotes



Table x: I2C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

-

Not connected.Input

Not used.

IN2-GNDInputNot used.

IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

IN4

-GNDInputI2C slave device address LSB.

IN5

-

Not connected.InputNot used.
IN6-GNDInputNot used.

CLK0A

CLK1_P

U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23OutputFPGA bank 45.
CLK1AMGT_CLK1_NU1, V5OutputFPGA MGT bank 225 reference clock.
CLK1BMGT_CLK1_PU1, V6OutputFPGA MGT bank 225 reference clock.
CLK2AMGT_CLK3_NU1, AB5OutputFPGA MGT bank 224 reference clock.
CLK2BMGT_CLK3_PU1, AB6OutputFPGA MGT bank 224 reference clock.
CLK3A

CLK0_P

U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25OutputFPGA bank 45.

 Table : Programmable quad PLL clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
........
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U16, pin 3.

Table : Reference clock signals.

On-board LEDs

LED ColorConnected toDescription and Notes
D1Green

........

Table : On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
VINTBD*
3.3VINTBD*

Table : Typical power consumption.


 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

Figure : Module power distribution diagram.


See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Notes
VIN1, 3, 52, 4, 6, 8InputMain supply voltage from the carrier board.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage supply. (would be good to add max. current allowed here if  possible)
B64_VCO9, 11-InputHR (High Range) bank voltage supply from the carrier board.

VBAT_IN

79-InputRTC battery supply voltage from the carrier board.
...............

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Note

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

Table : Module PL I/O bank voltages.

Board to Board Connectors

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4 x 5 SoMs - LSHM B2B Connectors
4 x 5 SoMs - LSHM B2B Connectors


Variants Currently In Production

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Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage



V

-

Storage temperature



°C

-

Table : Module absolute maximum ratings.


Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage



Operating temperature



Table : Module recommended operating conditions.


Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... mm.

  • PCB thickness: ... mm.

  • Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes



Table : Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
typeFlat

John Hartfiel
  • Rework chapter currently available products

v.60John Hartfiel
  • Remove Link to Download
2017-11-10
v.58
Ali Naseri
  • PDF-Link to online version of the TRM fixed
  • Online Link of download area fixed

2017-09-06

v.56
Jan Kumann
  • Template revision 1.64
  • SD Card interface added.


2017-09-02

v.54

Jan KumannDDR Memory section added.

2017-08-27

v.43

John Hartfiel
  • New template revision 1.6.
  • Moved Boot Process between Overview and Signals, Interfaces and Pins section.
2017-08-16v.42Jan Kumann
  • New template revision 1.5
  • MGT Lanes section changed.
  • Programmable PLL Clock section changed.
  • "Figure" and "Table" labels added.
  • Module variants and temperatures ranges sections improved.
  • Comments added/changed, also formatted as italic now.

2017-08-07

v.32

Jan KumannFew corrections and cosmetic changes.

2017-07-14

v.25

John Hartfiel

Removed weight section update template version

2017-06-08

v.20

John Hartfiel

Add revision number and update document change history

2017-05-30

v.1

Jan Kumann

Initial document.


all

Jan Kumann, John Hartfiel


Table : Document change history.

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