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The SD Card interface is connected to Bank bank 2 of the SoC
| FPGA / SoC Pin | Connected To | Signal Name | Notes |
|---|---|---|---|
| U2-H16 | J3-9 | SD_CD | Card detect switch |
| U2-N15 | J3-7 | SD_D0 | |
| U2-G18 | J3-8 | SD_D1 | |
| U2-R16 | J3-1 | SD_D2 | |
| U2-R17 | J3-2 | SD_D3 | |
| U2-R15 | J3-3 | SD_CMD | |
| U2-P15 | J3-5 | SD_CLK |
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On-board Gigabit Ethernet PHY (J2) is provided by Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to Bank bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).
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| Clock Source | Schematic Name | Frequency | Clock Destination |
|---|---|---|---|
| Crystal CX3225CA25000D0HSSCC | Y1 | 25.000 MHz1 | SmartFusion2 SoC U2 Main XTAL |
| Crystal ECX-31B | Y2 | 32.768 KHz | SmartFusion2 SoC U2 AUX XTAL |
| SiTime SiT8008AI oscillator | U11 | 25.000000 MHz | Gb Ethernet Copper PHY U1A |
| SiTime SiT8008AI oscillator | U14 | 25.000000 MHz | SmartFusion2 SoC U2-Y12 Bank 4 |
Table 9: Reference clock signals.
1In REV02, Y1 will be replaced by a 12 MHz crystal.
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