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FPGA SoC SignalPin

Pmod  Signal

Pmod Pin
MSIO71PB7U2-F3PB-01P1-1
MSIO71NB7U2-F4PB-02P1-2
MSIO68NB7U2-E3PB-03P1-3
MSIO80NB7U2-H4PB-04P1-4
MSIO75PB7U2-G4PB-05P1-7
MSIO75NB7U2-F5PB-06P1-8
MSIO67NB7U2-E5PB-07P1-9
MSIO78NB7U2-G3

PB-08

P1-10
MSIO79PB7U2-G1PC-01

P2-1

MSIO79NB7U2-F1PC-02P2-2
MSIO70NB7U2-E2PC-03P2-3
MSIO64PB7U2-C1PC-04P2-4
MSIO78PB7U2-G2PC-05P2-7
MSIO70PB7U2-E1PC-06P2-8
MSIO68PB7U2-D2

PC-07

P2-9
MSIO64NB7U2-C2

PC-08

P2-10
MSIO117NB4U2-Y16PA-01P3-1
MSIO117PB4U2-Y15PA-02P3-2
MSIO112PB4U2-W13PA-03P3-3
MSIO110PB4U2-V12PA-04P3-4
MSIO118PB4U2-W15PA-05P3-7
MSIO112NB4U2-W14PA-06P3-8
MSIO105NB4U2-Y13PA-07P3-9
MSIO104PB4U2-V11PA-08P3-10
MSIO4PB2U2-P20PD-01P4-1
MSIO3NB2U2-R20PD-02P4-2
MSIO2NB2U2-T19PD-03P4-3
MSIO0PB2U2-V20PD-04P4-4
MSIO6NB2U2-P19PD-05P4-7
MSIO3PB2U2-T20PD-06P4-8
MSIO1NB2U2-U19PD-07P4-9
MSIO0NB2U2-V19PD-08P4-10

Table 3: Overview of Pmod signals connected to the SoC.

JTAG Interface

JTAG access to the SoC components is provided through the micro usb connector via the FTDI usb to UART bridge. Depending on the jumper J6 the JTAGSEL signal SW3 switches the JTAG interface to either the FPGA fabric TAP (OPEN, high) or the Cortex-M3 JTAG debug interface (CLOSED, low). JTAG signals are powered by 3.3V.

FTDI signal

pin

JTAG Signal

Microsemi SmartFusion2 SoC pin

ADBUS0U3-12TCKU2-W19
ADBUS1U3-13TDIU2-V16
ADBUS2U3-14TDOU2-Y20
ADBUS3U3-15TMSU2-V17

Table 54: JTAG interface signals.

SD Card Interface

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FPGA / SoC PinConnected ToSignal NameNotes
U2-H16J3-9SD_CDCard detect switch
U2-N15J3-7SD_D0
U2-G18J3-8SD_D1
U2-R16J3-1SD_D2
U2-R17J3-2SD_D3
U2-R15J3-3SD_CMD
U2-P15J3-5SD_CLK

Table 65: SD Card interface signals and connections.

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PHY PinSignalMicrosemi SmartFusion2 SoC signalPinNotes
U1-25ETH_TXCKMSIOD84PB6U2-K7
U1-23

ETH_TXCTL

MSIOD87NB6U2-K3
U1-26ETH_TXD0MSIOD93PB6U2-L1
U1-28ETH_TXD1MSIOD97NB6U2-M2
U1-29ETH_TXD2MSIOD97PB6U2-M1
U1-30ETH_TXD3MSIOD95PB6U2-M3
U1-22ETH_RRXCKMSIOD84PB6U2-J2
U1-21ETH_RRXCTLMSIOD93NB6U2-K1
U1-20ETH_RRXD0MSIOD86PB6U2-K5

U1-18

ETH_RRXD1MSIOD82PB6

U2-H1


U1-17ETH_RRXD2MSIOD82NB6U2-H2
U1-16ETH_RRXD3MSIOD83PB6U2-J4
U1-31ETH_MDCMSIOD99PB6U2-N1
U1-33ETH_MDIOMSIOD99NB6U2-N2
U1-34

ETH_MDINT

MSIOD98PB6U2-N4
U1-35ETH_RSTMSIO114PB4U2-R13
U1-36PHY_RCLKOUTMSIO102NB4/CCC_NE1_CLKIOU2-W10
U1-39PHY_LED0MSIO104NB4U2-U11
U1-38PHY_LED1MSIO116PB4U2_T14

Table 76: Ethernet PHY signals and connections.

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I2C DeviceI2C AddressNotes
Header J80x50Device detection/identification.

Table 87: I2C slave device addresses.

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Clock SourceSchematic NameFrequencyClock Destination
Crystal CX3225CA25000D0HSSCCY1

25.000 MHz1

SmartFusion2 SoC U2 Main XTAL
Crystal ECX-31BY232.768 KHzSmartFusion2 SoC U2 AUX XTAL
SiTime SiT8008AI oscillatorU1125.000000 MHzGb Ethernet Copper PHY U1A
SiTime SiT8008AI oscillatorU1425.000000 MHz

SmartFusion2 SoC U2-Y12 Bank 4

Table 98: Reference clock signals.

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On-board LEDs

LED ColorConnected toSoC FPGA SignalDescription and Notes
D1RedU2-G16 Bank 1MSIO21PB1
D2GreenU2-G17 Bank 1MSIO21NB1
D3RGB

U2-H5 Bank 7, U2-F6 Bank 7, U2-H6 Bank 7

MSIO80PB7, MSIO67PB7, MSIO81NB7
J2Green, YellowU2-Y10 Bank 4, U2-U12 Bank 4MSIO102PB4, MSIO110NB4Ethernet: LED1A, LED1B
J2Green, YellowU2-V14 Bank 4, U2-U14 Bank 4MSIO115PB4, MSIO115PB4Ethernet: LED2A, LED2B

Table 109: On-board LEDs.

On-board Buttons

ButtonConnected toSoC FPGA Signal
S4U2-E17 Bank 1MSIO24PB1
S5U2-E16 Bank 1MSIO24NB1

Table 10: On-board Buttons.

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 Module VariantFPGA / SoC

Operating Temperature

Temperature Range
TEM0002-01M2S0100°C to +70°Ccommercial

Table 14: Module variants.

Technical Specifications

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Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.36.0

V

-

Storage temperature1

-25

70

°C

-

Table 15: Module absolute maximum ratings.

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ParameterMinMaxUnitsReference Document
VIN supply voltage2.45.5V-
Operating temperature1070°C-

Table 16: Module recommended operating conditions.

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All dimensions are given in millimeters.

Figure 4: Module physical dimensions drawing.

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DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes



Table 17: Module hardware revision history.

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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramNamePic_REV_number
simpleViewertrue
width200
linksauto
tbstyletop
lboxtrue
diagramWidth1571
revision3

Figure 5: Module hardware revision number.

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Date

Revision

Contributors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

  • initial document

all

Jan Kumann, John Hartfiel


Table 18: Document change history.

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