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Table of Contents

Table of Contents

Overview

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The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq-7010, which provides a dual core ARM Cortex A9 and a . It provides a gigabit ethernet transceiver, 1GByte of DDR3L SDRAM, 32 MByte Flash memory as configration and data storage. it includes strong pwerregulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

Key Features

  • Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I
    • Dual-core ARM Cortex-A9 MPCore
    • Max. 667 MHz
  • Shock proof and vibration resistant
  • Size 6 x 4 cm
  • Plug-On-Modul with 1 × 160 Pin High-Speed connector
  • 1 GByte DDR3L SDRAM
  • 32 MByte QSPI Flash Speicher
  • 1 x GBit Ethernet PHY
  • 1 x MAC-Address EEPROM
  • 128 KBit EEPROM
  • 1 x CAN Transceiver
  • On-Board DC/DC-regulators
  • Excellent signal integrity due to well dirstributed supply pins

Additional assembly options are available for cost or performance optimization upon request.

Block Diagramm

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Main Components

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  1. XILINX ZYNQ XC7Z020-2CLG400C, U1
  2. Gigabit Ethernet Transceiver Alaska 88E1512, U7
  3. Power Manager Dialog DA9062, U4
  4. 1GByte - 2x 4Gbit DDR3L RAM, U3, U5
  5. 32MByte Spansion SPI Flash S25FL256, U13
  6. 128KByte Serial EEPROM Microchip 24AA, U10
  7.  CAN Transceiver MCP2542FDT, U2
  8.  160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

Initial Delivery State

Storage device name

Content

Notes

Spansion SPI Flash S25FL256, U13

Empty


DA9062, U4Programmed
Microchip 24AA128T, U10EmptyUSER EEPROM
Microchip 24AA025E48T, U23MAC write protected preprogrammed, User area emptyEEPROM for MAC-Address.

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

Boot mode is selected via two pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card.

Boot mode

MODE1 J1-2

MODE0 J1-4

JTAG (cascade)LOWLOW
invalidLOWHIGH
SPIHIGHLOW
SD CARD (not on module)HIGHHIGH

Table 2: Boot mode selection.

Signals, Interfaces and Pins

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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

BankTypeB2B ConnectorI/O Signal CountBank VoltageNotes
500MIOJ18 I/Os3.3VOn-module power supply.
501MIOJ112 I/Os1.8VOn-module power supply.
34HRJ132 I/Os or 16 LVDS pairs3.3VOn-module power supply.
35HRJ148 I/Os or 24 LVDS pairsVCCIO_35Supplied by the carrier board.

Table 3: General overview of PL I/O signals connected to the B2B connectors.


All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIO40 to MIO51 depend on the carrier board peripherals connected to these pins.

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JTAG Interface

JTAG access to the ZYNQ SoC is provided through B2B connector J1 and testpoints.

JTAG Signal

B2B Connector Pin

TCKJ1-147
TDIJ1-151
TDOJ1-145
TMSJ1-149

Table 4: JTAG interface signals.

System Controller Pins

Special purpose pins are available for System Controller functions and are routed to the Power Management IC (U4) with the following default configuration:

Signal NameModeFunctionB2B Connector PinConfiguration
RESETREQINPUTReset requestJ1-150Aktive LOW, enter reset mode when set low. Pulled up to VIN.
ONKEYINPUTPower-on keyJ1-148Debounced edge sensitve power mode manipulator. On/Off with optional long press shutdown, function dependent on register value of NONKEY_PIN, KEY_DELAY.
PWR_TPIN/OUTTest pinJ1-146

Enables Power Commander boot mode and supply pin for OTP fusing voltage.

PWR_GPIO2IN/OUT
J1-143
PWR_GPIO2IN/OUT
J1-141

Table 5: System Controller CPLD I/O pins.


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Quad SPI Interface

Quad SPI Flash (U13) is connected to the Zynq PS QSPI_0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

MIOSignal NameU14 Pin
1SPI_CSC2
2SPI_DQ0/MIO2D3
3SPI_DQ1/MIO3D2
4SPI_DQ2/MIO4C4
5SPI_DQ3/MIO5D4
6SPI_SCK/MIO6B2

Table 6: Quad SPI interface signals and connections.

SD Card Interface

There is no physical SD Card slot on the module. Three different interface options are possible at a carrier via the PS MIO 10 to 15 or 40 to 45 or 46 to 51 plus additional MIOs for SD Card Detect and Write Protect as well as SD Card Power Controls. For details compare Xilinx UG585-Zynq-7000-TRM Table 2-4.

Ethernet Interface PHY


The TE0724 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U7) connected to PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the PL IO_L11P_T1_SRCC_34.

PHY PinPS bank 501B2BNotes
MDC/MDIOMIO52/MIO53-
LED0-J1-10
LED1-J1-12
LED2/Interrupt--not connected
CONFIG--connected to 1.8V (VDDO), PHY Address = 1
RESETnMIO39-
RGMIIMIO16..MIO27-
SGMII--not connected
MDI-J1-7,9,13,15,19,21,25,27

Table 7: Ethernet PHY connections.

CAN PHY

A felxible data rate CAN Transceiver is provided by a Microchip MCP2542FDT.

PHY PinPL bank 34B2BNotes
TX/RXIO_L1P/IO_L1N-
CAN_L / CAN_H-J1-1 / J1-3

I2C Interface

On-board I2C devices are connected to PS MIO28 (SCL) and MIO29 (SDA). I2C addresses for on-board devices are listed in the table below:

I2C Device7bit I2C AddressNotes
MAC EEPROM, U230x531.8V
USER EEPROM, U100x501.8V
Power Management U4 0x58 /  0x593.3V
J1
J1-142 SDA, J1-144 SDL at 3.3V

Table x: I2C slave device addresses.

On-board Peripherals

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Power Management IC

The Power Management IC (U4) is provided by dialog Semiconductors (DA9062). It controls the power-on sequencing of the various power rails. It is preprogrammed and accessible via I2C address 0x58 /  0x59.

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DDR Memory

By default TE0724 module has 2 DDR3L SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U13) on the TE0724-02 is a SPANSION S25FL256S with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.

USER EEPROM

A Microchip 24AA128T serial EEPROM (U10) is availabe for e.g. module idetification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I2C bus with slave device address 0x50.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic SignalFrequencyClock Destination
SiTime SiT8008BI oscillator, U9ETH_XTAL25.000000 MHzXTAL_IN,  U7 ETH PHY
SiTime SiT8008AI oscillator, U6PS_CLK33.333333 MHzPS_CLK_500, Bank 500

Table : Reference clock signals.

On-board LEDs

LED ColorConnected toDescription and Notes
D1GreenPS MIO7User LED.
D2GreenPL IO_L3P_T0_34User LED.
D3RedPL IO_L4N_T0_34User LED.

Table : On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
VINTBD*
3.3VINTBD*

Table : Typical power consumption.


 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available.

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies



Figure : Module power distribution diagram.


See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Notes
VIN1, 3, 52, 4, 6, 8InputMain supply voltage from the carrier board.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage supply. (would be good to add max. current allowed here if  possible)
B64_VCO9, 11-InputHR (High Range) bank voltage supply from the carrier board.

VBAT_IN

79-InputRTC battery supply voltage from the carrier board.
...............

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Note

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

Table : Module PL I/O bank voltages.

Board to Board Connectors

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4 x 5 SoMs - LSHM B2B Connectors


Variants Currently In Production

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Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage



V

-

Storage temperature



°C

-

Table : Module absolute maximum ratings.


Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage



Operating temperature



Table : Module recommended operating conditions.


Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... mm.

  • PCB thickness: ... mm.

  • Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes



Table : Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
typeFlat

John Hartfiel
  • Rework chapter currently available products

v.60John Hartfiel
  • Remove Link to Download

2017-05-30

v.1

Jan Kumann

Initial document.


all

Jan Kumann, John Hartfiel


Table : Document change history.

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