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The Trenz Electronic TEB0724-01 ... is an industrial-grade ... module ... based on Xilinx ...is a carrier board for the TE0724 and compatible modules.

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Refer to http://trenz.org/te0720teb0724-info for the current online version of this manual and other available documentation.

Key Features

  • Samtec 160 pin board to board connector
  • 10x 2x6 Pin  Pin Pmods, (4 8 usable as dual PmodPmods, 1x single Pmod, 1x I2C PMODPmod)
  • MicroUSB to JTAG/UART bridge
  • CAN screw terminal
  • RJ45 Gigabit Ethernet MagJack connector
  • 6x LED, 2x Push Button Buttons on FPGA
  • 1 LED and 1 Push button Button on PS
  • Power and Reset  Reset Push Buttons
  • On-board Power Protection Circuit and Power on LED

Block Diagram

put block diagram here ... like example block diagram below

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Main Components

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Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State


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Table 1: TE0724-01 main components.


Initial Delivery State

Not programmed.

Storage device name

Content

Notes

..

..

OTP Flash

Storage device name

Content

Notes

..

..

..OTP Flash
areaEmptyNot programmed.

Table 1: Initial delivery state of programmable devices on the module.

...

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

MODE Signal State

Boot Mode

High or open

SD Card

Low or ground

QSPI Interface

Table 2: Selecting power-on boot device.

...

I/O signals connected to the SoCs I/O bank and B2B connector: 

BankTypeB2B ConnectorI/O Signal CountBank VoltageNotes






64HRJM18 I/Os3.3VOn-module power supply.
66HPJM316 I/Os, 8 LVDS pairsB66_VCCOSupplied by the carrier board.

Table x: General overview of PL I/O signals connected to the B2B connectors.

...

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
0225GTH
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • MGTHRXP0_225, Y2
  • MGTHRXN0_225, Y1
  • MGTHTXP0_225, AA4
  • MGTHTXN0_225, AA3
1225GTH
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • MGTHRXP1_225, V2
  • MGTHRXN1_225, V1
  • MGTHTXP1_225, W4
  • MGTHTXN1_225, W3
............
4224GTH
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • JM1-12
  • JM1-10
  • JM1-6
  • JM1-4
  • MGTHRXP0_224, AH2
  • MGTHRXN0_224, AH1
  • MGTHTXP0_224, AG4
  • MGTHTXN0_224, AG3
5224GTH
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • JM1-24
  • JM1-22
  • JM1-18
  • JM1-16
  • MGTHRXP1_224, AF2
  • MGTHRXN1_224, AF1
  • MGTHTXP1_224, AF6
  • MGTHTXN1_224, AF5
............

Table x: MGT lanes.


Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
MGT_CLK0_P225B2B, JM3-33MGTREFCLK0P_225, Y6Supplied by the carrier board.
MGT_CLK0_N225B2B, JM3-31MGTREFCLK0N_225, Y5Supplied by the carrier board.
MGT_CLK1_P225U2, CLK1BMGTREFCLK1P_225, V6On-board Si5338A.
MGT_CLK1_N225U2, CLK1AMGTREFCLK1N_225, V5On-board Si5338A.
MGT_CLK2_P224B2B, JM3-34MGTREFCLK2P_224, AD6Supplied by the carrier board.
MGT_CLK2_N224B2B, JM3-32MGTREFCLK2N_224, AD5Supplied by the carrier board.
MGT_CLK3_P224U2, CLK2BMGTREFCLK3P_224, AB6On-board Si5338A.
MGT_CLK3_N224U2, CLK2BMGTREFCLK3N_224, AB5On-board Si5338A.

Table x: MGT reference clock sources.

...

JTAG access to the ... is provided through B2B connector .... 

JTAG Signal

B2B Connector Pin

TCKJMx-xx
TDIJMx-xx
TDOJMx-xx
TMSJMx-xx

Table 5: JTAG interface signals.

...

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionB2B Connector PinDefault Configuration
PGOODOutputPower GoodJ1-148Active high when all on-module power supplies are working properly.
JTAGENInputJTAG SelectJ2-131Low for normal operation.
..........

Table x: System Controller CPLD I/O pins.

...

Note that table column says "Signal Name", it should match the name used on the schematic.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table x: Quad SPI interface signals and connections.

...

Describe SD Card interface  shortly here if the module has one...

FPGA / SoC PinConnected ToSignal NameNotes
MIO0J10-9Card detect switch
MIO10J10-7DAT0
MIO11J10-3CMD
MIO12J10-5CLK
MIO13J10-8DAT1
MIO14J10-1DAT3
MIO15J10-2CD/DAT3

Table x: SD Card interface signals and connections.

...

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

PHY PinPSPLB2BNotes





Table x: ...

USB Interface

USB PHY is provided with ...

PHY PinPinB2B NameNotes




Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

...

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

I2C DeviceI2C AddressNotes



Table x: I2C slave device addresses.

...

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

-

Not connected.Input

Not used.

IN2-GNDInputNot used.

IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

IN4

-GNDInputI2C slave device address LSB.

IN5

-

Not connected.InputNot used.
IN6-GNDInputNot used.

CLK0A

CLK1_P

U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23OutputFPGA bank 45.
CLK1AMGT_CLK1_NU1, V5OutputFPGA MGT bank 225 reference clock.
CLK1BMGT_CLK1_PU1, V6OutputFPGA MGT bank 225 reference clock.
CLK2AMGT_CLK3_NU1, AB5OutputFPGA MGT bank 224 reference clock.
CLK2BMGT_CLK3_PU1, AB6OutputFPGA MGT bank 224 reference clock.
CLK3A

CLK0_P

U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25OutputFPGA bank 45.

 Table : Programmable quad PLL clock generator inputs and outputs.

...

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
........
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U16, pin 3.

Table : Reference clock signals.

On-board LEDs

LED ColorConnected toDescription and Notes
D1Green

........

Table : On-board LEDs.

Power and Power-On Sequence

...

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
VINTBD*
3.3VINTBD*

Table : Typical power consumption.

...

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Notes
VIN1, 3, 52, 4, 6, 8InputMain supply voltage from the carrier board.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage supply. (would be good to add max. current allowed here if  possible)
B64_VCO9, 11-InputHR (High Range) bank voltage supply from the carrier board.

VBAT_IN

79-InputRTC battery supply voltage from the carrier board.
...............

Table : Module power rails.

...

Note

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

Table : Module PL I/O bank voltages.

...

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Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage



V

-

Storage temperature



°C

-

Table : Module absolute maximum ratings.

...

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage



Operating temperature



Table : Module recommended operating conditions.

...

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes



Table : Module hardware revision history.

...

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
typeFlat

Ali Naseriupdated rules for draw.IO diagram



2018-

06

07-

18

02

v.

79Ali Naseri
  • Added new rule for draw.IO diagram with workaround for "Scroll PDF Exporter"
2018-06-13v.73
Martin Rohrmüller
  • nothing new (recreated destroyed document)

2018-05-09

v.63

John Hartfiel
  • Rework chapter currently available products

v.60John Hartfiel
  • Remove Link to Download
2017-11-10
v.58
Ali Naseri
  • PDF-Link to online version of the TRM fixed
  • Online Link of download area fixed

2017-09-06

v.56
Jan Kumann

2017-09-02

v.54

Jan KumannDDR Memory section added.

2017-08-27

v.43

John Hartfiel
  • New template revision 1.6.
  • Moved Boot Process between Overview and Signals, Interfaces and Pins section.
2017-08-16v.42Jan Kumann
  • New template revision 1.5
  • MGT Lanes section changed.
  • Programmable PLL Clock section changed.
  • "Figure" and "Table" labels added.
  • Module variants and temperatures ranges sections improved.
  • Comments added/changed, also formatted as italic now.

2017-08-07

v.32

Jan KumannFew corrections and cosmetic changes.

2017-07-14

v.25

John Hartfiel

Removed weight section update template version

2017-06-08

v.20

John Hartfiel

Add revision number and update document change history

2017-05-30

v.1

1

Jan Kumann

Initial document.

Table : Document change history.

...