Page History
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Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | 3.3V, VCCO_MIO0_500 | 3.3V | |
| 501 | 1.8V, VCCO_MIO1_501 | 1.8V | |
| 502 | 1.5V, VCCO_DDR_502 | 1.5V | |
| 0 Config | 3.3V | 3.3V | |
| 13 HR | VCCO13 | 1.2V to 3.3V | Supplied by the carrier board. |
| 33 HR | VCCIO33 | 1.2V to 3.3V | Supplied by the carrier board. |
| 34 HR | VCCIO34 | 1.2V 25V to 3.3V | Supplied by the carrier board. Minimum Voltage: B34 signals are used for CPLD/FPGA communication and for PG generated by (TPS3805H33DCKR) |
| 35 HR | VCCIO35 | 1.2V to 3.3V | Supplied by the carrier board. |
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