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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others	Notes
~~TE0820-ES1~~	es1 ~~es1~~	REV01	1GB	64		use slower DDR speed Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design for ES1
TE0820-02-2EG-1E	2eg_1e	REV02	1GB	64
TE0820-02-2EG-1E3	2eg_1e	REV02	1GB	64	2.5 mm Samtec connectors
TE0820-02-2EG-1EA	2eg_1e	REV02	1GB	128
TE0820-02-2EG-1EE	2eg_1ee	REV02	2GB	128
TE0820-02-2EG-1EL	2eg_1e	REV02	1GB	128	2.5 mm Samtec connectors
TE0820-02-2CG-1E	2cg_1e	REV02	1GB	64
TE0820-02-2CG-1EA	2cg_1e	REV02	1GB	128
TE0820-02-3EG-1E	3eg_1e	REV02	1GB	64
TE0820-02-3EG-1E3	3eg_1e	REV02	1GB	64	2.5 mm Samtec connectors
TE0820-02-3EG-1EA	3eg_1e	REV02	1GB	128
TE0820-02-3EG-1EL	3eg_1e	REV02	1GB	128	2.5 mm Samtec connectors
TE0820-02-3CG-1E	3cg_1e	REV02	1GB	64
TE0820-02-3CG-1EA	3cg_1e	REV02	1GB	128
TE0820-02-4CG-1EA	4cg_1e	REV02	1GB	128
TE0820-03-4EV-1EA	4ev_1e	REV03	1GB	128

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For SDK project creation, follow instructions from:

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2018.2 FSBL

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Date

Document Revision

Authors

Description

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	modified-date
	modified-date
dateFormat	yyyy-MM-dd

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prefix	v.

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	modified-user
	modified-user

add notes to ES1

06 Jul 2018

v.38

2018.2 release finished

19 Jun 2018

v.34

Design Files Update

13 Feb 2018

v.29

Design Files Update

2018-02-06

v.27

Design Files Update

2018-01-29

v.26

Update Known Issues

2018-01-24

v.25

Release 2017.4

2018-01-10

v.24

Update Known Issues

2017-12-20

v.23

Typo correction
Update HW Module Table Description

2017-11-21

v.19

Design Update

2017-11-20

v.18

Design Update
Add Variants with 128MB Flash

2017-11-13

v.16

Update Carrier sections

2017-11-06

v.15

Typo corrected

2017-10-23

v.13

Update Key Features section
Style Update Additional Software section

2017-10-19

v.9

Release 2017.2

2017-09-11

v.1

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Initial release

All

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