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Refer to https://wiki.trenz-electronic.de/display/PD/TE0782+TRM for online version of this manual and the rest of available documentation.

 



The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC (XC7Z035, XC7Z045 or XC7Z100).

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Block Diagram

Main Components

 

 


  1. Xilinx Zynq XC7Z SoC (XCZ035, XC7Z045 or XC7Z100), U1
  2. Lattice Semiconductor MachXO2 1200HC System Controller CPLD, U14
  3. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U19
  4. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U10
  5. Spansion 32 MByte QSPI Flash memory, U38
  6. SI5338A PLL programmable clock generator, U2
  7. TI low-dropout linear regulator @1.5V, U23
  8. Microchip USB3320C USB PHY transceiver, U8
  9. Microchip USB3320C USB PHY transceiver, U4

  10. Intersil ISL12020MIRZ Real Time Clock, U17

  11. LT quad 4A PowerSoC DC-DC converter (1.0V), U13

  12. LT quad 4A PowerSoC DC-DC converter (3.3V, 1,8V, 1.2V_MGT, 1.0V_MGT), U16

  13. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
  14. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
  15. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3

  16. Micron Technology 4 GByte eMMC, U15

  17. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
  18. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18

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Storage device nameContentNotes
24LC128-I/ST not programmedUser content

24AA025E48 EEPROM's

User content not programmed

Valid MAC Address from manufacturer
eMMC Flash-MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

 

SPI Flash main array

demo design

 


HyperFlash RAMnot programmed 

eFUSE USER

Not programmed 


eFUSE Security

Not programmed

 


Signals, Interfaces and Pins

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BankTypeVCCIO MaxConnectorIO countDifferentialIO VoltageNotes
10HR3.3VJ34422user 
11HR3.3VJ34020user 
12HR3.3VJ24020user 
13HR3.3VJ24020user 
33HP1.8VJ14823user 
34HP1.8VJ14220user 

For detailed information about the pin out, please refer to the Master pin-out table.

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NameConnectionNote
CLPD_GPIO7B2BFunction defined by CPLD Firmware (legacy name was BOOTMODE)
CLPD_GPIO6B2BFunction defined by CPLD Firmware (legacy name was CONFIGX)
JTAGENBB2BLogic high enables CPLD JTAG pins, when low CPLD JTAG access is disabled
nRST_INB2BActive low System-reset input (old name RESIN)
CLPD_GPIO0B2BFunction defined by CPLD Firmware
CLPD_GPIO1B2BFunction defined by CPLD Firmware
CLPD_GPIO2B2BFunction defined by CPLD Firmware
CLPD_GPIO3B2BFunction defined by CPLD Firmware
CLPD_GPIO4B2BFunction defined by CPLD Firmware
CLPD_GPIO5B2BFunction defined by CPLD Firmware
CPLD_IOPL 

Some of the functions of the SoM are controlled by the System Controller CPLD and it's firmware. User can change this by using(creating) different firmware for the System Controller CPLD.

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ClockFrequencyICZynq PS / PLNotes
PS CLK33.333333 MHzU61PS CLKPS subsystem main clock
ETH PHY reference25.000000 MHzU11-
USB PHY reference52.000000 MHzU7-

PLL reference

25.000000  MHz

U3

-

 


GT REFCLK1

-

B2B connector

Bank 110, pin AC7/AC8

Supplied from baseboard.

GT REFCLK4

-

B2B connector

Bank 111, pin U7/U8

Supplied from baseboard.

Si5338 CLK0 
U2Bank 110, pin AA8/AA7 
Si5338 CLK1 
U2Bank 109, pin AF10/AF9 
Si5338 CLK2 
U2Bank 111, pin W8/W7 
Si5338 CLK3 
U2Bank 112, pin N8/N7 

Default MIO Mapping

MIOConfigured asB2BNotes
0USB Reset -CPLD used as level translator
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7Ethernet Reset -CPLD used level translator
8UART TXJC3:129output, muxed to B2B by the SC CPLD
9UART RXJC3:135input, muxed to B2B by the SC CPLD
10SDIO1 D0--
11SDIO1 CMD--
12SDIO1 CLK--
13SDIO1 D1--
14SDIO1 D2--
15SDIO1 D3--
16..27ETH0-Ethernet RGMII PHY
28..39USB0-USB0 ULPI PHY
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO--

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PHY PINZYNQ PS / PLSystem Controller CPLDNotes
MDC/MDIOMIO52, MIO53--
LED0BANK35, Pin B12--
LED1BANK35, Pin C12--
InterruptBANK35, Pin A15--
CONFIGBANK35, Pin F14--
RESETn-Pin 53ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
RGMIIMIO16..MIO27 
-
MDI--on B2B J2 connector

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DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53user data, parameter
EEPROM24AA025E48T-I/OTU220x50MAC address EEPROM
EEPROM24AA025E48T-I/OTU240x51MAC address EEPROM
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57Integrated in RTC
PLLSI5338A-B-GMRU20x70 
CPLDLCMXO2-1200HC-4TG100IU14user-

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PeripheralICDesignatorZynq PS / PLMIONotes
QSPI FlashS25FL256SAGBHI20U38PS QSPI0MIO1...MIO6-
ETH0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U18PS ETH0MIO16...MIO27, MIO52, MIO53-
ETH0 10/100/1000 Mbps PHY Reset  

PS GPIOMIO7ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
ETH1 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U20BANK9, BANK35-PHY can be used with soft Ethernet MAC IP also
ETH1 10/100/1000 Mbps PHY Reset  

BANK35, Pin B15--
USB0USB3320C-EZKU4PS USB0MIO28...MIO39-
USB0 Reset  

PS GPIOMIO0OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET
USB1USB3320C-EZKU8USB1MIO40...MIO51-
USB1 Reset  

PS GPIOMIO0OTG_RESET33 (MIO0)  -> CPLD -> OTG_RESET
Clock PLLSi5338U2BANK35, Pin L14/L15 
Low jitter phase locked loop
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U15SDIO0MIO10...MIO15-
HyperFlash RAMS26KS512SDPBHI00xU9BANK35-

optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)

or optional 2 x 64 MByte HyperFLASH

HyperFlash RAMS26KS512SDPBHI00xU12BANK35-as above
EEPROM I2C24LC128-I/STU26BANK35, Pin L14/L15--
EEPROM I2C24AA025E48T-I/OTU22BANK35, Pin L14/L15-MAC Address
EEPROM I2C24AA025E48T-I/OTU24BANK35, Pin L14/L15-MAC Address
RTCISL12020MIRZU17BANK35, Pin L14/L15-Temperature compensated real time clock
RTC InterruptISL12020MIRZU17--RTC_INT -> CPLD
UART  

PS UARTMIO8, MIO9forwarded to B2B by SC CPLD

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ParameterMinMaxUnitsNotes

VIN supply voltage

-0.3

15

V

 

VIN33 supply voltage

-0.5

3.75

V


VBAT supply voltage-0.36V
PL IO Bank supply voltage for HR I/O banks (VCCO)-0.53.6V 
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55V 

Voltage on module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 3.3V nominal

Storage temperature

-40

+85

C

 
Storage temperature without the ISL12020MIRZ-55+100C 
Note
Assembly variants for higher storage temperature range on request

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ParameterMinMaxUnitsNotesReference document
VIN supply voltage11.412.6V 

VIN33 supply voltage3.1353.465V 

VBAT supply voltage12.855.5V  

PL IO Bank supply voltage for HR I/O banks (VCCO)1.143.465V 
Xilinx document DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheetXilinx document DS191 and DS187
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 
Note
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).

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Date RevisionChanges
2015-05-27

02

First production release


 01Prototypes

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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DateRevisionContributorsDescription
2018-05-15
Ali Nasericorrected minimum recommended VBAT supply voltage
2018-01-31


v21


Ali Naseriupdated Power section, added diagramms
2017-06-07


v19


Jan KumannMinor formatting
2017-05-23
V13
 


Jan Kumann

New block diagram.

New product images.

New physical dimensions drawing.

2017-01-24

V12 


Ali Naseri

New numbered pictures describing main components.

Added variants in production.

2016-06-27v10Ali Naseri, Jan KumannInitial release.

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