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See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.
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| Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | |||||||||
| EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | |||||||||
| EN_PL | J2-101 | PL_DCIN | left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | External pull-up needed (max. voltage GT_DCDC), max. sink current 1 mA | TPS82085SIL / | |||||||||
| EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | |||||||||
| EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |||||||||
| EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74401 data sheet | EN_GT_L | J2-79 | GT_DCDC | NC7S08P5X data sheet | PG_GT_L | J2-97 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |
| EN_PLL_PWR | J2-77 | 6V | TPS82085SIL data sheet | PG_PLL_1V8 | J2-80 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS82085SIL data sheet |
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