Page History
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| Signal | B2B Connector Pin | Function |
|---|---|---|
| PLL_FINC | J2-81 | Frequency increment |
| PLL_LOLN | J2-85 | Loss of lock (active-low) |
| PLL_SEL0 / PLL_SEL1 | J2-93 / J2-87 | Manual input switching |
| PLL_FDEC | J2-94 | Frequency decrement |
| PLL_RST | J2-89 | Device reset (active-low) |
| PLL_SCL / PLL_SDA | J2-90 / J2-92 | I2C interface, external pull-ups needed for SCL / SDA lines I2C address in current configuration: 1101000b. |
Table 1214: B2B connector pin-out of Si5345A programmable clock generator.
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| Clock | Signal Schematic Name | Frequency | Connected to Bank 503 Pin |
|---|---|---|---|
| MEMS Oscillator, U32 | PS_CLK | 33.333333 MHz | Bank 503 Pin P20 |
| Quartz crystal, Y2 | XTALI / XTALO | 32.768 kHz | Bank 503 Pin R22/R23 |
| Quartz crystal, Y1 | XAXB_P / XAXB_N | 50.000 MHz | PLL U5, Pin XA/XB |
Table 1315: On-board osciallators
MAC Address EEPROMs
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LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Red | DONE signal (PS Configuration Bank 503) | This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly. |
Table 1416: LED's description.
Power and Power-On Sequence
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| Power Input Pin | Typical Current |
|---|---|
| DCDCIN | TBD* |
| LP_DCDC | TBD* |
| PL_DCIN | TBD* |
| PS_BATT | TBD* |
Table 1517: Maximum current of power supplies. *to be determined soon with reference design setup.
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| Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | |
|---|---|---|---|---|---|---|---|---|
| EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | |
| EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | |
| EN_PL | J2-101 | PL_DCIN | left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | 4K7, pulled up to PL_DCIN | - | |
| EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | |
| EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |
| EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74401 data sheet | |
| EN_PLL_PWR | J2-77 | 6V | TPS82085SIL data sheet | PG_PLL_1V8 | J2-80 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS82085SIL data sheet |
Table 1618: Recommended operation conditions of DC-DC converter control signals.
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Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | B2B J4 Pins | Directions | Note |
|---|---|---|---|---|---|---|
| PL_DCIN | 151, 153, 157, 159 | - | - | - | Input | - |
| DCDCIN | - | 154, 156, 158, 160, | - | - | Input | - |
| LP_DCDC | - | 138, 140, 142, 144 | - | - | Input | - |
| PS_BATT | - | 125 | - | - | Input | - |
| GT_DCDC | - | - | 157, 158, 159, 160 | - | Input | - |
| PLL_3V3 | - | - | 152 | - | Input | U5 (programmable PLL) 3.3V nominal input |
| SI_PLL_1V8 | - | - | 151 | - | Output | Internal voltage level 1.8V nominal output |
| PS_1V8 | - | 99 | 147, 148 | - | Output | Internal voltage level |
| PL_1V8 | 91, 121 | - | - | - | Output | Internal voltage level |
| DDR_1V2 | - | 135 | - | - | Output | Internal voltage level |
| VCCO47 | - | - | 43, 44 | - | Input | - |
| VCCO48 | - | - | 15, 16 | - | Input | - |
| VCCO64 | - | - | - | 58, 106 | Input | - |
| VCCO65 | - | - | - | 69, 105 | Input | - |
| VCCO66 | 90, 120 | - | - | - | Input | - |
Table 1719: TE0807-02 power rails
Bank Voltages
| Bank | Type | Schematic Name | Voltage | Reference Input Voltage | Voltage Range |
|---|---|---|---|---|---|
| 47 | HD | VCCO47 | user | - | 1.2V to 3.3V |
| 48 | HD | VCCO48 | user | - | 1.2V to 3.3V |
| 64 | HP | VCCO64 | user | VREF_64, pin J4-88 | 1.2V to 1.8V |
| 65 | HP | VCCO65 | user | VREF_65, pin J4-15 | 1.2V to 1.8V |
| 66 | HP | VCCO66 | user | VREF_66, pin J1-108 | 1.2V to 1.8V |
| 500 | MIO | PS_1V8 | 1.8V | - | - |
| 501 | MIO | PS_1V8 | 1.8V | - | - |
| 502 | MIO | PS_1V8 | 1.8V | - | - |
| 503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 1820: TE0807-02 I/O bank voltages
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Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | -0.3 | 7 | V | TPS82085SIL / EN63A0QI data sheet |
| DCDCIN | -0.3 | 7 | V | TPS82085SIL / TPS51206 data sheet |
| LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
| GT_DCDC | -0.3 | 7 | V | TPS82085SIL data sheet |
| PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
| PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
| VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| MGT clock absolute input voltage | -0.5 | 1.3 | V | Xilinx document DS925 |
MGT Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
| "Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Table 1921: Module absolute maximum ratings
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| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | 3.3 | 6 | V | EN63A0QI / TPS82085SIL data sheet |
| DCDCIN | 3.3 | 6 | V | TPS82085SIL / TPS51206PSQ data sheet |
| LP_DCDC | 3.3 | 3.6 | V | TPS82085SIL / TPS3106 data sheet |
| GT_DCDC | 3.3 | 6 | V | TPS82085SIL data sheet |
| PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
| PLL_3V3 | 3.3 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
| VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PL bank reference voltage VREF pin | -0.5 | 2 | V | Xilinx DS925 data sheet |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
Table 2022: Recommended operating conditions
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| Date | Revision | Notes | PCN Link | Documentation Link |
|---|---|---|---|---|
| - | 02 | current available module revision | - | TE0807-02 |
| - | 01 | first production release | - | TE0807-01 |
Table 2123: Hardware revision history table
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Table 2124: Document change history
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