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I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J2:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J2	I/O	48	24	FPGA Bank 12 HR	FMC_VADJ	Bank voltage FMC_VADJ is supplied by DC-DC converter U7
		34	17	FPGA Bank 13 HR	FMC_VADJ
		34	17	FPGA Bank 15 HR	FMC_VADJ
		44	44	FPGA Bank 16 HR	VIO_B_FMC	Bank voltage VIO_B_FMC is supplied by FMC connector J2
	I²C	2	-	SC CPLD U5, Bank 2, pin 48, 49	-	FMC connector J2 is hardware programmed to I²C address 0x50
	JTAG	5	-	SC CPLD U5, Bank 2, pin 27, 28, 331, 32 ,36	3.3V	-
	MGT	-	8 (4 x RX/TX)	Bank 116 GTX	-	4x MGT lanes
	Clock Input	-	2	Bank 116 GTX	-	2x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U5, Bank 1, pin 68, 69 ,70	3.3V	'FMC_PG_C2M', 'FMC_PG_M2C', 'FMC_PRSNT_M2C_L'

Table 2: FMC connector J2 interface

For detailed information about the pin out, please refer to the Pin-out Tables.

FMC connector J2 MGT Lanes:

FMC	MGT Lane	Bank	Type	Signal Schematic Name	FMC Connector Pin	FPGA Pin
J2	0	116	GTX	DP3_M2C_P DP3_M2C_N DP3_C2M_P DP3_C2M_N	J2-A10 J2-A11 J2-A30 J2-A31	MGTXRXP0_116, G4 MGTXRXN0_116, G3 MGTXTXP0_116, F2 MGTXTXN0_116, F1
	1	116	GTX	DP2_M2C_P DP2_M2C_N DP2_C2M_P DP2_C2M_N	J2-A6 J2-A7 J2-A26 J2-A27	MGTXRXP1_116, E4 MGTXRXN1_116, E3 MGTXTXP1_116, D2 MGTXTXN1_116, D1
	2	116	GTX	DP1_M2C_P DP1_M2C_N DP1_C2M_P DP1_C2M_N	J2-A2 J2-A3 J2-A22 J2-A23	MGTXRXP2_116, C4 MGTXRXN2_116, C3 MGTXTXP2_116, B2 MGTXTXN2_116, B1
	3	116	GTX	DP0_M2C_P DP0_M2C_N DP0_C2M_P DP0_C2M_N	J2-C6 J2-C7 J2-C2 J2-C3	MGTXRXP3_116, B6 MGTXRXN3_116, B5 MGTXTXP3_116, A4 MGTXTXN3_116, A3

Table 3: FMC connector J2 MGT lanes

FMC connector J2 reference clock sources:

FMC	Signal Schematic Name	Connected to	FMC Connector Pin	FPGA Pin	Notes
J2	GBTCLK0_M2C_P GBTCLK0_M2C_N	MGT bank 116	J2-D4 J2-D5	MGTREFCLK0P_116, D6 MGTREFCLK0N_116, D5	Supplied by attached FMC module
J2	GBTCLK1_M2C_P GBTCLK1_M2C_N	MGT bank 116	J2-B20 J2-B21	MGTREFCLK1P_116, F6 MGTREFCLK1N_116, F5	Supplied by attached FMC module

Table 4: FMC connector J2 clock signal input

FMC connector J2 VCC/VCCIO:

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J2	3V3FMC	J2-D36 J2-D38 J2-D40 J2-C39	DCDC U15, max. current: 4A	Enable by SC CPLD U5, bank 1, pin 60 Signal: 'EN_3V3FMC'
	3V3	J2-D32	LDO U9, max. current: 0.5A	not dedicated for FMC connector
	12V	J2-C35 J2-C37	external source through ATX main power connector	-
	FMC_VADJ	J2-H40 J2-G39 J2-F40 J2-E39	DCDC U7, max. current: 6A	Enable by SC CPLD U5, bank 1, pin 51 Signal: 'EN_FMC_VADJ' set voltage FMC_VADJ by DIP switch S1

Table 5: FMC connector J2 available VCC/VCCIO

FMC connector J2 Cooling Fan:

FMC	Fan Designator	Enable Signal	Notes
J2	M1	Enable by SC CPLD U5, bank 0, pin 78 Signal: 'FAN_FMC_EN'	-

Table 6: FMC connector J2 cooling fan

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Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

PCIe	Lane	Bank	Type	Signal Name	PCIe Connector Pin	FPGA Pin
J1	0	115	GTX	PER3_P PER3_N PET3_P PET3_N	J1-A29 J1-A30 J1-B27 J1-B28	MGTXTXP0_115, P2 MGTXTXN0_115, P1 MGTXRXP0_115, R4 MGTXRXN0_115, R3
	1	115	GTX	PER2_P PER2_N PET2_P PET2_N	J1-A25 J1-A26 J1-B23 J1-B24	MGTXTXP1_115, M2 MGTXTXN1_115, M1 MGTXRXP1_115, N4 MGTXRXN1_115, N3
	2	115	GTX	PER1_P PER1_N PET1_P PET1_N	J1-A21 J1-A22 J1-B19 J1-B20	MGTXTXP2_115, K2 MGTXTXN2_115, K1 MGTXRXP2_115, L4 MGTXRXN2_115, L3
	3	115	GTX	PER0_P PER0_N PET0_P PET0_N	J1-A16 J1-A17 J1-B14 J1-B15	MGTXTXP3_115, H2 MGTXTXN3_115, H1 MGTXRXP3_115, J4 MGTXRXN3_115, J3

Table 7: GTX lanes routed to the PCIe interface

PCIe	Signal Schematic Name	Connected to	PCIe connector pin	FPGA Pin	Notes
J1	PCIE_CLK_P PCIE_CLK_N	MGT bank 115	J1-A13, REFCLK+ J1-A14, REFCLK-	MGTREFCLK1P_115, K6 MGTREFCLK1N_115, K5	External clock supplied by PCIe interface

Table 8: PCIe reference clock sources

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JTAG Interface	Signal Schematic Name	JTAG Connector Pin	Connected to
CPLD JTAG VCCIO: 3.3V Connector: J8	CPLD_JTAG_TMS	J8-1	SC CPLD, bank 0, pin 90
	CPLD_JTAG_TDI	J8-2	SC CPLD, bank 0, pin 94
	CPLD_JTAG_TDO	J8-3	SC CPLD, bank 0, pin 95
	CPLD_JTAG_TCK	J8-4	SC CPLD, bank 0, pin 91

FPGA JTAG VCCIO: 1.8V Connector: J9	FPGA_JTAG_TMS	J9-4	FPGA, bank 0, pin N9
	FPGA_JTAG_TCK	J9-6	FPGA, bank 0, pin M8
	FPGA_JTAG_TDO	J9-8	FPGA, bank 0, pin N8
	FPGA_JTAG_TDI	J9-10	FPGA, bank 0, pin L8

Table 59: JTAG interface signals

FAN Connectors

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Connector	Schematic net names	Connected to	Notes
4-Wire PWM FAN connector J4, 12V power supply	'F1SENSE', pin 3 'F1PWM', pin 4	SC CPLD U5, pin 99 SC CPLD U5, pin 98	FPGA cooling FAN can be controlled via I²C interface from FPGA, see current SC CPLD firmware
2-pin FAN connector J6, 5V power supply with TPS2051 Load Switch U25	'FAN_FMC_EN', U25 pin 4	SC CPLD U5, pin 78	FMC cooling FAN

Table 910: FAN connectors

On-board Peripherals

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Pin Name	SC CPLD Direction	Function	Default Configuration
200MHZCLK_EN	out	control line	enables 200.0000MHz oscillator U1
BUTTON	in	user	Reset Button
CPLD_TDO	out	CPLD JTAG interface	-
CPLD_TDI	in
CPLD_TCK	in
CPLD_TMS	in
JTAG_EN	in
DDR3_SCL	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
DDR3_SDA	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
PLL_SCL	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PLL_SDA	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PCIE_RSTB	in	PCIe reset input	see current SC CPLD firmware
FEX_DIR / FEX0 ... FEX11	in / out	user GPIO	see current SC CPLD firmware
F1PWM	out	FPGA FAN control	see current SC CPLD firmware
F1SENSE	in	FPGA FAN control
FAN_FMC_EN	out	FMC FAN enable
FMC_PG_C2M	out	FMC signals and pins	see current SC CPLD firmware
FMC_PG_M2C	in
FMC_PRSNT_M2C_L	in
FMC_SCL	in / out	FMC I²C	I²C connected to FPGA
FMC_SDA	in / out	FMC I²C	I²C connected to FPGA
FMC_TCK		FMC JTAG	see current SC CPLD firmware
FMC_TDI
FMC_TDO
FMC_TMS
FMC_TRST
DONE	in	FPGA configuration signal	PL configuration completed
PROGRAM_B	out	FPGA configuration signal	PL configuration reset signal
LED1	out	LED status signal	see current CPLD firmware
FPGA_IIC_OE	in	SC CPLD works as I²C switch with the FPGA as I²C-Master and on-board peripherals as I²C-slaves	I²C output enable, connected to PL bank 14 pin F25
FPGA_IIC_SCL	in / out		I²C clock line, connected to PL bank 14 pin G26
FPGA_IIC_SDA	in / out		I²C data line, connected to PL bank 14 pin G25
EN_1V8	out	Power control	enable signal DCDC U20 '1V8'
PG_1V8	in		power good signal DCDC U20 '1V8'
EN_3V3FMC	out		enable signal DCDC U15 'EN_3V3FMC'
PG_3V3	in		power good signal U15 'EN_3V3FMC'
EN_FMC_VADJ	out		enable signal DCDC U7 'FMC_VADJ'
PG_FMC_VADJ	in		power good DCDC U7 'FMC_VADJ'
VID0_FMC_VADJ, VID1_FMC_VADJ, VID2_FMC_VADJ	out		DCDC U7 power selection pin
VID0_FMC_VADJ_CTRL, VID1_FMC_VADJ_CTRL, VID2_FMC_VADJ_CTRL	in		Power selection of FMC_VADJ, forwarded to DCDC U7
LTM_1V5_RUN	out		enable signals of DCDC U3, U4 (LTM4676) see current CPLD firmware
LTM_4V_RUN	out
LTM_SCL	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM_SDA	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM1_ALERT	in	DCDC U3, U4 (LTM4676) control	see current CPLD firmware
LTM2_ALERT	in
LTM_1V_IO0	in / out
LTM_1V_IO1	in / out
LTM_1V5_4V_IO0	in / out
LTM_1V5_4V_IO1	in / out

Table 611: System Controller CPLD I/O pins

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I²C Interface	Schematic net names	Connected to	I²C Address	Notes
DDR3 SODIMM, U2	'DDR3_SDA', pin 200 'DDR3_SCL', pin 202	SC CPLD U5, pin 42 SC CPLD U5, pin 43	module dependent	-

Table 812: DDR3 SODIMM socket I²C interface

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Signal Name	QSPI Flash Memory U12 Pin	FPGA Pin
FLASH_QSPI_CS	S, Pin 7	Bank 14, Pin C23
FLASH_QSPI_D00	DQ0, Pin 15	Bank 14, Pin B24
FLASH_QSPI_D01	DQ1, Pin 8	Bank 14, Pin A25
FLASH_QSPI_D02	DQ2, Pin 9	Bank 14, Pin B22
FLASH_QSPI_D03	DQ3, Pin 1	Bank 14, Pin A22
FPGA_CFG_CCLK	C, Pin 16	Bank 0, Pin C8

Table 713: Quad SPI interface signals and connections

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Si5338A Pin	Signal Name / Description	Connected to	Direction	Note
IN1	-	not connected	Input	not used
IN2	-	GND	Input	not used
IN3	Reference input clock	U3, pin 3	Input	25.000000 MHz oscillator U14, Si8208AI
IN4	-	GND	Input	I²C slave device address LSB
IN5	-	not connected	Input	not used
IN6	-	GND	Input	not used
SCL	PLL_SCL	SC CPLD U5, pin 8	Input / Output	I²C interface muxed to FPGA Slave address: 0x70.
SDA	PLL_SDA	SC CPLD U5, pin 2	Input / Output	I²C interface muxed to FPGA Slave address: 0x70.
CLK0A	CLK0_P	U6, G24	Output	Clock to PL bank 14
CLK0B	CLK0_N	U6, F24	Output	Clock to PL bank 14
CLK1A	MGTCLK_5338_P	U6, H6	Output	Clock to MGT bank 115, AC decoupled
CLK1B	MGTCLK_5338_N	U6, H5	Output	Clock to MGT bank 115, AC decoupled
CLK2A	CLK1_P	U6, G22	Output	Clock to PL bank 14
CLK2B	CLK1_N	U6, F23	Output	Clock to PL bank 14
CLK3A	CLK2_P	U6, D23	Output	Clock to PL bank 14
CLK3B	CLK2_N	U6, D24	Output	Clock to PL bank 14

Table 1014: Programmable quad PLL clock generator inputs and outputs

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Clock Source	Frequency	Signal Schematic Name	Clock Destination	Notes
U14, SiT8208AI	25.000000 MHz	CLK	Si5338A PLL U13, pin 3 (IN3)	-
U1, DSC1123DL5	200.0000 MHz	DDR3_CLK_P	FPGA bank 33, pin AB11	Enable by SC CPLD U5, pin 30 Signal: '200MHzCLK_EN'
U1, DSC1123DL5	200.0000 MHz	DDR3_CLK_N	FPGA bank 33, pin AC11	Enable by SC CPLD U5, pin 30 Signal: '200MHzCLK_EN'
FMC Connector J2	-	GBTCLK0_M2C_P, Pin J2-D4	FPGA bank 116, pin D6	reference clock to MGT bank 116
	-	GBTCLK0_M2C_N, Pin J2-D5	FPGA bank 116, pin D5	reference clock to MGT bank 116
	-	GBTCLK1_M2C_P, Pin J2-B20	FPGA bank 116, pin F6	reference clock to MGT bank 116
	-	GBTCLK1_M2C_N, Pin J2-B21	FPGA bank 116, pin F5	reference clock to MGT bank 116
	-	CLK0_M2C_P, Pin J2-H4	FPGA bank 15, pin H17	reference clock to PL bank 15
	-	CLK0_M2C_N, Pin J2-H5	FPGA bank 15, pin H18	reference clock to PL bank 15
	-	CLK1_M2C_P, Pin J2-G2	FPGA bank 15, pin G17	reference clock to PL bank 15
	-	CLK1_M2C_N, Pin J2-G3	FPGA bank 15, pin G18	reference clock to PL bank 15
	-	CLK2_BIDIR_P, Pin J2-K4	FPGA bank 13, pin P23	reference clock to PL bank 13 bidirectional clock line
	-	CLK2_BIDIR_N, Pin J2-K5	FPGA bank 13, pin N23	reference clock to PL bank 13 bidirectional clock line
	-	CLK3_BIDIR_P, Pin J2-J2	FPGA bank 13, pin R22	reference clock to PL bank 13 bidirectional clock line
	-	CLK3_BIDIR_N, Pin J2-J3	FPGA bank 13, pin R23	reference clock to PL bank 13 bidirectional clock line

Table 1115: Reference clock signals

On-board LEDs

LED	Color	Signal Schematic name	Connected to	Description and Notes
D1	Green	FPGA_LED1_VT	FPGA bank 13, pin K25	LEDs D1 to D10 are available to user. LED voltages are translated from bank voltage FMC_VADJ to 3V3.
D2	Green	FPGA_LED2_VT	FPGA bank 13, pin K26
D3	Green	FPGA_LED3_VT	FPGA bank 13, pin P26
D4	Green	FPGA_LED4_VT	FPGA bank 13, pin R26
D5	Green	FPGA_LED5_VT	FPGA bank 13, pin N16
D6	Green	FPGA_LED6_VT	FPGA bank 14, pin J26
D7	Green	FPGA_LED7_VT	FPGA bank 14, pin H26
D8	Green	FPGA_LED8_VT	FPGA bank 14, pin E26
D9	Green	FPGA_LED9_VT	FPGA bank 14, pin A24
D10	Green	FPGA_LED10_VT	FPGA bank 15, pin F19
D11	Green	LED1	System Controller CPLD, bank 0, pin 76	see current CPLD firmware for LED functionality

Table 1216: On-board LEDs

Configuration DIP-switch

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DIP-switch S3	Signal Schematic Name	Connected to	Functionality	Notes
S1-1	JTAG_EN	SC CPLD U5, bank 1, pin 82	enables JTAG interface of SC CPLD U5	SC CPLD programmable through JTAG connector, J8
S1-2	VID0_FMC_VADJ_CTRL	SC CPLD U5, bank 1, pin 71	set 3-bit code to set FMC_VADJ voltage	The FMC_VADJ voltage is provided by DCDC U7 EN5365QI, the voltage can be set from 0.8V to 3.3V in 7 steps: Set DIP-switches as bit pattern S1-4 \| S1-3 \| S1-2: FMC_VADJ 0 \| 0 \| 0 : 3.3V 0 \| 0 \| 1 : 2.5V 0 \| 1 \| 0 : 1.8V 0 \| 1 \| 1 : 1.5V 1 \| 0 \| 0 : 1.25V 1 \| 0 \| 1 : 1.2V 1 \| 1 \| 0 : 0.8V 1 \| 1 \| 1 : Reserved
S1-3	VID1_FMC_VADJ_CTRL	SC CPLD U5, bank 1, pin 63
S1-4	VID2_FMC_VADJ_CTRL	SC CPLD U5, bank 1, pin 62

Table 1317: DIP-switch S1 functionality description

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LTM4676 U3 pin	Schematic net names	Connected to	Notes
SDA, pin D6 SCL, pin E6	'LTM_SDA' 'LTM_SCL'	SC CPLD U5, pin 66 SC CPLD U5, pin 67	I²C Address: 0x40 I²C interface of LTM4676 also accessible with header J10
ALERT, pin E5	'LTM2_ALERT'	SC CPLD U5, pin 64	active low
GPIO0, pin E4	'LTM_1V5_4V_IO0'	SC CPLD U5, pin 85	active low
GPIO1, pin F4	'LTM_1V5_4V_IO1'	SC CPLD U5, pin 83	active low
LTM4676 U4 pin	Schematic net names	Connected to	Notes
SDA, pin D6 SCL, pin E6	'LTM_SDA' 'LTM_SCL'	SC CPLD U5, pin 66 SC CPLD U5, pin 67	I²C Address: 0x4F I²C interface of LTM4676 also accessible with header J10
ALERT, pin E5	'LTM1_ALERT'	SC CPLD U5, pin 65	active low
GPIO0, pin E4	'LTM_1V_IO0'	SC CPLD U5, pin 86	active low
GPIO1, pin F4	'LTM_1V_IO1'	SC CPLD U5, pin 88	active low

Table 818: DCDC converters U3 and U4 I/O's and interfaces

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Power Input	Typical Current
12V VIN	TBD*

Table 1419: Typical power consumption

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Bank	Schematic Name	Voltage	Range	Notes
0	1V8	1.8V	-	Config bank 0 fixed to 1.8V
12	FMC_VADJ	user	HR: 1.2V to 3.3V	FMC_VADJ voltage ajustable by DIP switch S1
13	FMC_VADJ	user	HR: 1.2V to 3.3V	FMC_VADJ voltage ajustable by DIP switch S1
14	1V8	1.8V	HR: 1.2V to 3.3V	PL bank 14 fixed to 1.8V
15	FMC_VADJ	user	HR: 1.2V to 3.3V	FMC_VADJ voltage ajustable by DIP switch S1
16	VIO_B_FMC	user	HR: 1.2V to 3.3V	PL bank 16 fixed to 1.8V
32	1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
33	1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
34	1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
115 116	MGTAVCC_FPGA MGTVCCAUX_FPGA MGTAVTT_FPGA	1.0V 1.8V 1.2V	MGT bank supply voltage MGT bank auxiliary supply voltage MGT bank termination circuits voltage	MGT banks with Xilinx GTX transceiver units

Table 1520: Board I/O bank voltages

Power Rails

Connector / Pin	Voltage	Direction	Notes
J4, pin 2	12V	Output	4-wire PWM fan connector supply voltage
J6, pin 2	5V	Output	Cooling fan M1 supply voltage
J8, pin 6	3V3	Output	VCCIO CPLD JTAG
J9, pin 2	1V8	Output	VCCIO FPGA JTAG
J2, pin C35 / C37	12V	Output	FMC supply voltage
J2, pin D32	3V3	Output	VCCIO FMC
J2, pin D36 / D38 / D39 / D40	3V3FMC	Output	VCCIO FMC
J2, pin H1	VREF_A_M2C	Input	VREF voltage for bank 13 / 15
J2, pin K1	VREF_B_M2C	Input	VREF voltage for bank 16
J2, pin J39 / J40	VIO_B_FMC	Input	PL I/O voltage bank 16 (VCCO)
J2, pin H40 / G39 / F40 / E39	FMC_VADJ	Output	PL I/O voltage bank 12 / 13 / 15 (VCCO)
J1, pin B1 / B2 / B3 / A2 / A3	12V_input_B	Input	12V main power supply from PCIe connector
J5, pin 1 / 2 / 3	12V_input_A	Input	Main power supply connector

Table 1621: Board power rails

Variants Currently In Production

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.3	20	V	TPS6217 datasheet Caution with Note: voltage limitations are not valid for connected FMC module plugged in and/or FPGA FAN connected:VIN range then 11.4V ... 12.6V
Supply voltage for HR I/O banks (VCCO)	-0.500	3.600	V	Xilinx datasheet DS182
Supply voltage for HP I/O banks (VCCO)	-0.500	2.000	V	Xilinx datasheet DS182
I/O input voltage for HR I/O banks	-0.500	VCCO + 0.500	V	Xilinx datasheet DS182
I/O input voltage for HP I/O banks	-0.500	VCCO + 0.500	V	Xilinx datasheet DS182
Reference Voltage pin (VREF)	-0.500	2	V	Xilinx datasheet DS182
Differential input voltage	-0.5	2.625	V	Xilinx datasheet DS182
I/O input voltage for SC CPLD U5	-0.5	3.75	V	Lattice MachXO2 Family datasheet
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)	-0.500	1.320	V	Xilinx datasheet DS182
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.500	1.260	V	Xilinx datasheet DS182
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10	-0.3	5.5	V	LTM4676A datasheet
Storage temperature	-40	+100	°C	SML-P11 LED datasheet

Table 1722: Module absolute maximum ratings

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	11.4	12.6	V	12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)	1.140	3.465	V	Xilinx datasheet DS182
Supply voltage for HP I/O banks (VCCO)	1.140	1.890	V	Xilinx datasheet DS182
I/O input voltage for HR I/O banks	-0.500	VCCO + 0.20	V	Xilinx datasheet DS182
I/O input voltage for HP I/O banks	-0.500	VCCO + 0.20	V	Xilinx datasheet DS182
Differential input voltage	-0.2	2.625	V	Xilinx datasheet DS182
I/O input voltage for SC CPLD U5	-0.3	3.6	V	Lattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10	0	3.3V	V	LTM4676A datasheet
Board Operating Temperature Range ^{1), 2)}	-40	85	°C	FPGA SoC has industrial grade temperature range (Xilinx datasheet DS182), board operating temperature range limited by on-board peripherals

Table 23Table 18: Module recommended operating conditions

1) The operating temperature range depends also on assembly options of the variants

2) The operating temperature range of the FPGA chip is the junction temperature

Board Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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Date	Revision	Notes	PCN	Documentation Link
-	02	current available board revision	-	-
-	01	First production release	PCN-20180524 TEF1001-01	TEF1001-01

Table 1924: Module hardware revision history

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

Initial document

Table 2025: Document change history

Disclaimer

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Trenz Electronic Documentation

Versions Compared

Old Version 23

New Version 24

Key

FAN Connectors

On-board Peripherals

On-board LEDs

Configuration DIP-switch

Power Rails

Variants Currently In Production

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