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Pin NameSC CPLD DirectionFunctionDefault Configuration
200MHZCLK_ENoutcontrol lineenables 200.0000MHz oscillator U1
BUTTONinuserReset Button
CPLD_TDOoutCPLD JTAG interface



-
CPLD_TDIin
CPLD_TCKin
CPLD_TMSin
JTAG_ENin
DDR3_SCLin / outI²C bus of DDR3 SODIMM socket

I²C connected to FPGA
DDR3_SDAin / out
PLL_SCLin / outI²C bus of SI5338 quad clock PLLI²C connected to FPGA
PLL_SDAin / out
PCIE_RSTBinPCIe reset inputsee current SC CPLD firmware
FEX_DIR / FEX0 ... FEX11in / outuser GPIOsee current SC CPLD firmware
F1PWMoutFPGA FAN controlsee current SC CPLD firmware
F1SENSEin
FAN_FMC_ENoutFMC FAN enable
FMC_PG_C2MoutFMC signals and pinssee current SC CPLD firmware
FMC_PG_M2Cin
FMC_PRSNT_M2C_Lin
FMC_SCLin / outFMC I²CI²C connected to FPGA
FMC_SDAin / out
FMC_TCK
FMC JTAGsee current SC CPLD firmware
FMC_TDI
FMC_TDO
FMC_TMS
FMC_TRST
DONEinFPGA configuration signalPL configuration completed
PROGRAM_BoutPL configuration reset signal
LED1outLED status signalsee current CPLD firmware
FPGA_IIC_OEinSC CPLD works as I²C switch
with the FPGA as I²C-Master
and on-board peripherals as
I²C-slaves		I²C output enable, connected to PL bank 14 pin F25
FPGA_IIC_SCLin / outI²C clock line, connected to PL bank 14 pin G26
FPGA_IIC_SDAin / outI²C data line, connected to PL bank 14 pin G25
EN_1V8outPower controlenable signal DCDC U20 '1V8'
PG_1V8inpower good signal DCDC U20 '1V8'
EN_3V3FMCoutenable signal DCDC U15 'EN_3V3FMC'
PG_3V3inpower good signal U15 'EN_3V3FMC'
EN_FMC_VADJoutenable signal DCDC U7 'FMC_VADJ'
PG_FMC_VADJinpower good DCDC U7 'FMC_VADJ'

VID0_FMC_VADJ,
VID1_FMC_VADJ,
VID2_FMC_VADJ

outDCDC U7 power selection pin

VID0_FMC_VADJ_CTRL,
VID1_FMC_VADJ_CTRL,
VID2_FMC_VADJ_CTRL

inPower selection of FMC_VADJ, forwarded
to DCDC U7
LTM_1V5_RUNoutenable signals of DCDC U3, U4 (LTM4676)
see current CPLD firmware
LTM_4V_RUNout
LTM_SCLin / outDCDC U3, U4 (LTM4676) I²C

I²C

connected to FPGA

Address U3: 0x40

I²C Address U4: 0x4F

I²C interface of LTM4676 ICs
also accessible through header J10

LTM_SDAin / out
LTM1_ALERTinDCDC U3, U4 (LTM4676) control,
active low		see current CPLD firmware
LTM2_ALERTin
LTM_1V_IO0in / out
LTM_1V_IO1in / out
LTM_1V5_4V_IO0in / out
LTM_1V5_4V_IO1in / out

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DIP-switch S3Signal Schematic NameConnected toFunctionalityNotes
S1-1JTAG_ENSC CPLD U5, bank 1, pin 82enables JTAG interface of SC CPLD U5SC CPLD programmable through JTAG connector, J8
S1-2VID0_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 71set 3bit code to adjust FMC_VADJ voltage

The FMC_VADJ voltage is provided by DCDC U7 EN5365QI,

the voltage can be adjusted from 0.8V to 3.3V in 7 steps:

Set DIP-switches as  bit pattern "S1-4 | S1-3 | S1-2:  FMC_VADJ":

0 | 0 | 0 :   3.3V
0 | 0 | 1 :   2.5V
0 | 1 | 0 :   1.8V
0 | 1 | 1 :   1.5V
1 | 0 | 0 :   1.25V
1 | 0 | 1 :   1.2V
1 | 1 | 0 :   0.8V
1 | 1 | 1 :   Reserved

S1-3VID1_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 63
S1-4VID2_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 62

Table 17: DIP-switch S1 functionality description

DC-DC Converters

On-board DC-DC converters U3 (1V5 and 4V) and U4 (1V) are provided by Linear Technology LTM4676 with special I/O's and I²C interface:

...

'LTM_SDA'
'LTM_SCL'

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SC CPLD U5, pin 66
SC CPLD U5, pin 67

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I²C Address: 0x40

I²C interface of LTM4676
also accessible through header J10

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SDA, pin D6
SCL, pin E6

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'LTM_SDA'
'LTM_SCL'

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SC CPLD U5, pin 66
SC CPLD U5, pin 67

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I²C Address: 0x4F

I²C interface of LTM4676
also accessible through header J10

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8V
1 | 1 | 1 :   Reserved

S1-3VID1_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 63
S1-4VID2_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 62

Table 17: DIP-switch S1 functionality descriptionTable 18: DCDC converters U3 and U4 I/O's and interfaces

Power and Power-On Sequence

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Power InputTypical Current
12V VINTBD*

Table 1918: Typical power consumption

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BankSchematic NameVoltageRangeNotes
01V81.8V-Config bank 0 fixed to 1.8V
12FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
13FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
141V81.8VHR: 1.2V to 3.3VPL bank 14 fixed to 1.8V
15FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
16VIO_B_FMCuserHR: 1.2V to 3.3VPL bank 16 fixed to 1.8V
321V51.5VHP: 1.2V to 1.8VDDR3 memory interface
331V51.5VHP: 1.2V to 1.8VDDR3 memory interface
341V51.5VHP: 1.2V to 1.8VDDR3 memory interface

115

116

MGTAVCC_FPGA

MGTVCCAUX_FPGA

MGTAVTT_FPGA

1.0V

1.8V

1.2V

MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTX transceiver units

Table 2019: Board I/O bank voltages

Power Rails

Connector / PinVoltageDirectionNotes
J4, pin 212VOutput4-wire PWM fan connector supply voltage
J6, pin 25VOutputCooling fan M1 supply voltage
J8, pin 63V3OutputVCCIO CPLD JTAG
J9, pin 21V8OutputVCCIO FPGA JTAG
J2, pin C35 / C3712VOutputFMC supply voltage
J2, pin D323V3OutputVCCIO FMC
J2, pin D36 / D38 / D39 / D403V3FMCOutputVCCIO FMC
J2, pin H1VREF_A_M2CInputVREF voltage for bank 13 / 15
J2, pin K1VREF_B_M2CInputVREF voltage for bank 16
J2, pin J39 / J40VIO_B_FMCInputPL I/O voltage bank 16 (VCCO)
J2, pin H40 / G39 / F40 / E39FMC_VADJOutputPL I/O voltage bank 12 / 13 / 15 (VCCO)
J1, pin B1 / B2 / B3 / A2 / A312V_input_BInput12V main power supply from PCIe connector
J5, pin 1 / 2 / 312V_input_AInputMain power supply connector

Table 2120: Board power rails

Variants Currently In Production

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Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.320

V

TPS6217 datasheet

Note: voltage limitations are not valid for connected FMC module and/or FPGA FAN

Supply voltage for HR I/O banks (VCCO)

-0.500

3.600

VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)

-0.500

2.000VXilinx datasheet DS182
I/O input voltage for HR I/O banks

-0.500

VCCO + 0.500

VXilinx datasheet DS182

I/O input voltage for HP I/O banks

-0.500

VCCO + 0.500

VXilinx datasheet DS182
Reference Voltage pin (VREF)-0.5002VXilinx datasheet DS182
Differential input voltage-0.52.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.53.75VLattice MachXO2 Family datasheet
GTX transceiver reference clocks absolute input voltage-0.5001.320VXilinx datasheet DS182

GTX transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage

-0.500

1.260

VXilinx datasheet DS182
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10-0.35.5VLTM4676A datasheet

Storage temperature

-40

+100

°C

SML-P11 LED datasheet

Table 2221: Module absolute maximum ratings

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ParameterMinMaxUnitsReference Document
VIN supply voltage11.412.6V12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)1.140

3.465

VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)

1.140

1.890

VXilinx datasheet DS182

I/O input voltage for HR I/O banks

-0.500

VCCO + 0.20VXilinx datasheet DS182
I/O input voltage for HP I/O banks-0.500VCCO + 0.20VXilinx datasheet DS182
Differential input voltage-0.22.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.33.6VLattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J1003.3VVLTM4676A datasheet

Board Operating Temperature Range 1), 2)

-4085°C

board operating temperature range limited by FPGA SoC and on-board peripherals

Table 2322: Module recommended operating conditions

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DateRevision

Notes

PCNDocumentation Link
-02current available board revision--
-

01

First production release

PCN-20180524 TEF1001-01TEF1001-01

Table 2423: Module hardware revision history

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Initial document

Table 2524: Document change history

Disclaimer

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