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Control Signals
To get started with TEF1001 board, some basic control signals are essential and are described in the following table:
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For detailed information, refer to the reference page of the SC CPLD firmware of this module. Table below lists the SC CPLD I/O pins with their default configuration:
| Pin Name | SC CPLD DirectionU5 Pins and Interfaces | Connected to | Function | Default ConfigurationNotes |
|---|---|---|---|---|
| 200MHZCLK_ENout | Oscillator U1, pin 1 | control line | enables 200.0000MHz oscillator U1 | |
| BUTTONin | Push Button S2 | user | Reset Button | |
| CPLD_JTAG_TDO | out | header J8, pin 3 | SC CPLD JTAG interface | SC CPLD JTAG interface enabled when DIP-switch S1-1 in ON-position |
| CPLD_JTAG_TDI | inheader J8, pin 2 | |||
| CPLD_JTAG_TCK | inheader J8, pin 4 | |||
| CPLD_JTAG_TMS | inheader J8, pin 1 | |||
| JTAG_ENin | DIP switch S1-1 | |||
| DDR3_SCLin / out | SO-DIMM U2. pin 202 | I²C bus of DDR3 SODIMM SO-DIMM socket | I²C bus connected to FPGA | |
| DDR3_SDAin / out | SO-DIMM U2. pin 200 | |||
| PLL_SCLin / out | Si5338 U13, pin 12 | I²C bus of SI5338 quad clock PLL | I²C bus connected to FPGA | |
| PLL_SDAin / out | Si5338 U13, pin 19 | |||
| PCIE_RSTBRSTb | PCIe J1, pin A11in | PCIe reset input | refer to current SC CPLD firmware for functionality | |
| FEX_DIR / FEX0 ... FEX11in / out | FPGA bank 14 | user GPIO | refer to current SC CPLD firmware for functionality | |
| F1PWMout | FAN connector J4, pin 4 | FPGA FAN control | refer to current SC CPLD firmware for functionality | |
| F1SENSE | in | |||
| FAN_FMC_EN | out | FMC FAN enable | ||
| FMC_PG_C2M | out | FMC signals and pins | refer to current SC CPLD firmware for functionality | |
| FMC_PG_M2C | in | |||
| FMC_PRSNT_M2C_L | in | |||
| FMC_SCL | in / out | FMC I²C | I²C connected to FPGA | |
| FMC_SDA | in / out | |||
| FMC_TCK | FMC JTAG | refer to current SC CPLD firmware for functionality | ||
| FMC_TDI | ||||
| FMC_TDO | ||||
| FMC_TMS | ||||
| FMC_TRST | ||||
| DONE | in | FPGA configuration signal | PL configuration completed | |
| PROGRAM_B | out | PL configuration reset signal | ||
| LED1 | out | LED status signal | refer to current SC CPLD firmware for functionality | |
| FPGA_IIC_OE | in | SC CPLD works as I²C switch with the FPGA as I²C-Master and on-board peripherals as I²C-slavesSlaves | I²C output enable, connected to PL bank 14 pin F25 | |
| FPGA_IIC_SCL | in / out | I²C clock line, connected to PL bank 14 pin G26 | ||
| FPGA_IIC_SDA | in / out | I²C data line, connected to PL bank 14 pin G25 | ||
| EN_1V8 | out | Power control | enable signal DCDC U20 '1V8' | |
| PG_1V8 | in | power good signal DCDC U20 '1V8' | ||
| EN_3V3FMC | out | enable signal DCDC U15 'EN_3V3FMC' | ||
| PG_3V3 | in | power good signal U15 'EN_3V3FMC' | ||
| EN_FMC_VADJ | out | enable signal DCDC U7 'FMC_VADJ' | ||
| PG_FMC_VADJ | in | power good DCDC U7 'FMC_VADJ' | ||
VID0_FMC_VADJ, | out | DCDC U7 power selection pin | ||
VID0_FMC_VADJ_CTRL, | in | Power selection of FMC_VADJ, forwarded to DCDC U7 | ||
| LTM_1V5_RUN | out | enable signals of DCDC U3, U4 (LTM4676) refer to current SC CPLD firmware for functionality | ||
| LTM_4V_RUN | out | |||
| LTM_SCL | in / out | DCDC U3, U4 (LTM4676) I²C | I²C Address U3: 0x40 I²C Address U4: 0x4F I²C interface of LTM4676 ICs | |
| LTM_SDA | in / out | |||
| LTM1_ALERT | in | DCDC U3, U4 (LTM4676) control, active low | refer to current SC CPLD firmware for functionality | |
| LTM2_ALERT | in | |||
| LTM_1V_IO0 | in / out | |||
| LTM_1V_IO1 | in / out | |||
| LTM_1V5_4V_IO0 | in / out | |||
| LTM_1V5_4V_IO1 | in / out |
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| LED | Color | Signal Schematic name | Connected to | Description and Notes |
|---|---|---|---|---|
| D1 | Green | FPGA_LED1_VT | FPGA bank 13, pin K25 | LEDs D1 to D10 are available to user. LED voltages are translated from FPGA bank 13 and 14 |
| D2 | Green | FPGA_LED2_VT | FPGA bank 13, pin K26 | |
| D3 | Green | FPGA_LED3_VT | FPGA bank 13, pin P26 | |
| D4 | Green | FPGA_LED4_VT | FPGA bank 13, pin R26 | |
| D5 | Green | FPGA_LED5_VT | FPGA bank 13, pin N16 | |
| D6 | Green | FPGA_LED6_VT | FPGA bank 14, pin J26 | |
| D7 | Green | FPGA_LED7_VT | FPGA bank 14, pin H26 | |
| D8 | Green | FPGA_LED8_VT | FPGA bank 14, pin E26 | |
| D9 | Green | FPGA_LED9_VT | FPGA bank 14, pin A24 | |
| D10 | Green | FPGA_LED10_VT | FPGA bank 15, pin F19 | |
| D11 | Green | LED1 | System Controller CPLD, bank 0, pin 76 | see refer to current CPLD firmware for LED functionality |
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| DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes |
|---|---|---|---|---|
| S1-1 | JTAG_EN | SC CPLD U5, bank 1, pin 82 | enables JTAG interface of SC CPLD U5 in ON-position | SC CPLD programmable through JTAG connector, header J8 |
| S1-2 | VID0_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 71 | set 3bit code to adjust FMC_VADJ voltage | The FMC_VADJ voltage is provided by DCDC U7 EN5365QI, the voltage can be adjusted from 0.8V to 3.3V in 7 steps: Set DIP-switches as bit pattern "S1-4 | S1-3 | S1-2: FMC_VADJ": 0 | 0 | 0 : 3.3V |
| S1-3 | VID1_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 63 | ||
| S1-4 | VID2_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 62 |
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