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Scroll Title
anchorTable_SIP_FMC_Interface
titleFMC connector J2 interfaces

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InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4824FPGA Bank 12 HRFMC_VADJBank voltage FMC_VADJ is supplied by DC-DC converter U7
3417FPGA Bank 13 HRFMC_VADJ
3417FPGA Bank 15 HRFMC_VADJ
4444FPGA Bank 16 HRVIO_B_FMCBank voltage VIO_B_FMC is supplied by FMC connector J2
I²C2-SC CPLD U5, Bank 2, pin 48, 49-FMC connector J2 is hardware programmed to I²C address 0x50
JTAG5-SC CPLD U5, Bank 2, pin 27, 28, 331, 32 ,363.3V4 JTAG pins with additional signal 'TRST'
MGT-8 (4 x RX/TX)Bank 116 GTX-4x MGT lanes
Clock Input-2Bank 116 GTX-2x Reference clock input to MGT bank
Control Signals3-SC CPLD U5, Bank 1, pin 68, 69 ,703.3V

'FMC_PG_C2M', 'FMC_PG_M2C', 'FMC_PRSNT_M2C_L'

For detailed information about the pin out, please refer to the Pin-out Tables.

FMC connector J2 MGT Lanes:

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anchorTable_SIP_FMC_MGT
titleFMC connector J2 MGT lanes

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MGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin
0116GTX
  • DP3_M2C_P
  • DP3_M2C_N
  • DP3_C2M_P
  • DP3_C2M_N
  • J2-A10
  • J2-A11
  • J2-A30
  • J2-A31
  • MGTXRXP0_116, G4
  • MGTXRXN0_116, G3
  • MGTXTXP0_116, F2
  • MGTXTXN0_116, F1
1116GTX
  • DP2_M2C_P
  • DP2_M2C_N
  • DP2_C2M_P
  • DP2_C2M_N
  • J2-A6
  • J2-A7
  • J2-A26
  • J2-A27
  • MGTXRXP1_116, E4
  • MGTXRXN1_116, E3
  • MGTXTXP1_116, D2
  • MGTXTXN1_116, D1
2116GTX
  • DP1_M2C_P
  • DP1_M2C_N
  • DP1_C2M_P
  • DP1_C2M_N
  • J2-A2
  • J2-A3
  • J2-A22
  • J2-A23
  • MGTXRXP2_116, C4
  • MGTXRXN2_116, C3
  • MGTXTXP2_116, B2
  • MGTXTXN2_116, B1
3116GTX
  • DP0_M2C_P
  • DP0_M2C_N
  • DP0_C2M_P
  • DP0_C2M_N
  • J2-C6
  • J2-C7
  • J2-C2
  • J2-C3
  • MGTXRXP3_116, B6
  • MGTXRXN3_116, B5
  • MGTXTXP3_116, A4
  • MGTXTXN3_116, A3


FMC connector J2 reference clock sources:

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anchorTable_SIP_FMC_CLK
titleFMC connector J2 clock signal input

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Signal Schematic NameConnected toFMC Connector PinFPGA PinNotes
  • GBTCLK0_M2C_P
  • GBTCLK0_M2C_N
MGT bank 116

J2-D4
J2-D5

MGTREFCLK0P_116, D6
MGTREFCLK0N_116, D5

Supplied by attached FMC module
  • GBTCLK1_M2C_P
  • GBTCLK1_M2C_N
MGT bank 116J2-B20
J2-B21
MGTREFCLK1P_116, F6
MGTREFCLK1N_116, F5
Supplied by attached FMC module


FMC connector J2 VCC/VCCIO:

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anchorTable_SIP_FMC_VCCIO
title FMC connector J2 available VCC/VCCIO

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Available VCC/VCCIOFMC Connector PinSourceNotes
3V3FMC

J2-D36
J2-D38
J2-D40
J2-C39

DCDC U15,
max. current: 4A

Enable by SC CPLD U5, bank 1, pin 60
Signal: 'EN_3V3FMC'

3V3

J2-D32

LDO U9,

max. current: 0.5A
not dedicated for FMC connector
12V

J2-C35
J2-C37

external source through
ATX main power connector

-
FMC_VADJ

J2-H40
J2-G39
J2-F40
J2-E39

DCDC U7,
max. current: 6A

Enable by SC CPLD U5, bank 1, pin 51
Signal: 'EN_FMC_VADJ'

set voltage FMC_VADJ by DIP switch S1


FMC connector J2 Cooling Fan:

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anchorTable_SIP_FMC_FAN
titleFMC connector J2 cooling fan

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Fan DesignatorEnable SignalNotes
M1

Enable by SC CPLD U5, bank 0, pin 78
Signal: 'FAN_FMC_EN'

-

PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2 with 4 GTX lanes routed to the PCIe interface.

Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

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anchorTable_SIP_PCIE_GTX
titleGTX lanes routed to the PCIe interface

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LaneBankTypeSignal NamePCIe Connector PinFPGA Pin
0115GTX
  • PER3_P
  • PER3_N
  • PET3_P
  • PET3_N
  • J1-A29
  • J1-A30
  • J1-B27
  • J1-B28
  • MGTXTXP0_115, P2
  • MGTXTXN0_115, P1
  • MGTXRXP0_115, R4
  • MGTXRXN0_115, R3
1115GTX
  • PER2_P
  • PER2_N
  • PET2_P
  • PET2_N
  • J1-A25
  • J1-A26
  • J1-B23
  • J1-B24
  • MGTXTXP1_115, M2
  • MGTXTXN1_115, M1
  • MGTXRXP1_115, N4
  • MGTXRXN1_115, N3
2115GTX
  • PER1_P
  • PER1_N
  • PET1_P
  • PET1_N
  • J1-A21
  • J1-A22
  • J1-B19
  • J1-B20
  • MGTXTXP2_115, K2
  • MGTXTXN2_115, K1
  • MGTXRXP2_115, L4
  • MGTXRXN2_115, L3
3115GTX
  • PER0_P
  • PER0_N
  • PET0_P
  • PET0_N
  • J1-A16
  • J1-A17
  • J1-B14
  • J1-B15
  • MGTXTXP3_115, H2
  • MGTXTXN3_115, H1
  • MGTXRXP3_115, J4
  • MGTXRXN3_115, J3



Scroll Title
anchorTable_SIP_PCIE_CLK
titlePCIe reference clock sources

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PCIeSignal Schematic NameConnected toPCIe connector pinFPGA PinNotes

J1

  • PCIE_CLK_P
  • PCIE_CLK_N
MGT bank 115

J1-A13, REFCLK+
J1-A14, REFCLK-

MGTREFCLK1P_115, K6
MGTREFCLK1N_115, K5

External clock supplied by PCIe interface

JTAG Connectors

There are two JTAG connectors J8 and J9 available on the TEF1001 board:

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anchorTable_SIP_JTAG
titleJTAG interface signals

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JTAG InterfaceSignal Schematic NameJTAG Connector PinConnected to

CPLD JTAG

VCCIO: 3.3V

Connector: J8

CPLD_JTAG_TMSJ8-1SC CPLD, bank 0, pin 90
CPLD_JTAG_TDIJ8-2SC CPLD, bank 0, pin 94
CPLD_JTAG_TDOJ8-3SC CPLD, bank 0, pin 95
CPLD_JTAG_TCK

J8-4

SC CPLD, bank 0, pin 91




FPGA JTAG

VCCIO: 1.8V

Connector: J9

FPGA_JTAG_TMSJ9-4FPGA, bank 0, pin N9
FPGA_JTAG_TCKJ9-6FPGA, bank 0, pin M8
FPGA_JTAG_TDOJ9-8FPGA, bank 0, pin N8
FPGA_JTAG_TDIJ9-10FPGA, bank 0, pin L8

FAN Connectors

The TEF1001 board offers one FAN connector for cooling the FPGA device and one built-in FAN for the FMC modules.

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anchorTable_SIP_FAN_Connector
titleFAN connectors

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ConnectorSignal Schematic NamesConnected toNotes
4-Wire PWM FAN
connector J4,
12V power supply

'F1SENSE', pin J4-3
'F1PWM', pin J4-4

SC CPLD U5, pin 99
SC CPLD U5, pin 98

FPGA cooling FAN can be controlled via
I²C interface from FPGA,
see current SC CPLD firmware
2-pin FAN connector J6,
5V power supply
with TPS2051 Load Switch U25

'FAN_FMC_EN',

(Load Switch U25, pin 4)

SC CPLD U5, pin 78

FMC cooling FAN

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

Scroll Title
anchorTable_OBP_SC_CPLD
titleSystem Controller CPLD I/O pins

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SC CPLD U5 Pins and InterfacesConnected toFunctionNotes
200MHZCLK_ENOscillator U1, pin 1Oscillator U1 control lineenables 200.0000MHz oscillator U1
BUTTONPush Button S2userReset Button
CPLD_JTAG_TDOheader J8, pin 3SC CPLD JTAG interfaceSC CPLD JTAG interface enabled when
DIP-switch S1-1 in ON-position
CPLD_JTAG_TDIheader J8, pin 2
CPLD_JTAG_TCKheader J8, pin 4
CPLD_JTAG_TMSheader J8, pin 1
JTAG_ENDIP switch S1-1
DDR3_SCLSO-DIMM U2. pin 202I²C bus of DDR3 SO-DIMMI²C interface connected to FPGA
DDR3_SDASO-DIMM U2. pin 200
PLL_SCLSi5338 U13, pin 12I²C bus of SI5338 quad clock PLLI²C interface connected to FPGA
PLL_SDASi5338 U13, pin 19
PCIE_RSTbPCIe J1, pin A11PCIe reset inputrefer to current SC CPLD firmware for functionality
FEX_DIR / FEX0 ... FEX11FPGA bank 14user GPIOrefer to current SC CPLD firmware for functionality
F1PWMFAN connector J4, pin 4FPGA FAN controlrefer to current SC CPLD firmware for functionality
F1SENSEFAN connector J4, pin 3
FAN_FMC_ENLoad Switch U25, pin 4FMC FAN enable
FMC_PG_C2MFMC J2, pin D1FMC control signalsrefer to current SC CPLD firmware for functionality
FMC_PG_M2CFMC J2, pin F1
FMC_PRSNT_M2C_LFMC J2, pin H2
FMC_SCLFMC J2, pin C30FMC I²CI²C connected to FPGA
FMC_SDAFMC J2, pin C31
FMC_TCKFMC J2, pin D29FMC JTAGrefer to current SC CPLD firmware for functionality
FMC_TDIFMC J2, pin D30
FMC_TDOFMC J2, pin D31
FMC_TMSFMC J2, pin D33
FMC_TRSTFMC J2, pin D34
DONEFPGA bank 0, pin J7FPGA configuration signalPL configuration completed
PROGRAM_BFPGA bank 0, pin P6PL configuration reset signal
LED1Green LED D11LED status signalrefer to current SC CPLD firmware for functionality
FPGA_IIC_OEFPGA bank 14, pin F25SC CPLD works as I²C switch
with the FPGA as I²C-Master
and on-board peripherals as
I²C-Slaves
I²C output enable
FPGA_IIC_SCLFPGA bank 14, pin G26I²C clock line
FPGA_IIC_SDAFPGA bank 14, pin G25I²C data line
EN_1V8DC-DC U20, pin 27Power controlenable signal DC-DC U20
PG_1V8DC-DC U20, pin 28power good signal DC-DC U20
EN_3V3FMCDC-DC U15, pin 27enable signal DC-DC U15
PG_3V3DC-DC U15, pin 28power good signal DC-DC U15
EN_FMC_VADJDC-DC U7, pin 52enable signal DC-DC U7
PG_FMC_VADJDC-DC U7, pin 46power good DC-DC U7

VID0_FMC_VADJ,
VID1_FMC_VADJ,
VID2_FMC_VADJ

DC-DC U7, pin 45, 44, 43DCDC U7 power selection pin

VID0_FMC_VADJ_CTRL,
VID1_FMC_VADJ_CTRL,
VID2_FMC_VADJ_CTRL

DIP switch S1-2,
DIP switch S1-3,
DIP switch S1-4
Power selection of FMC_VADJ, forwarded
to DCDC U7
LTM_1V5_RUNDC-DC U3, pin F5enable signals of DCDC U3, U4 (LTM4676)
refer to current SC CPLD firmware for functionality
LTM_4V_RUNDC-DC U3, pin F5
LTM_SCLDC-DC U3 / U4, pin E6DCDC U3, U4 (LTM4676) I²C

I²C Address U3: 0x40

I²C Address U4: 0x4F

I²C interface of LTM4676 ICs
also accessible through header J10

LTM_SDADC-DC U3 / U4, pin D6
LTM1_ALERTDC-DC U4, pin E5DCDC U3, U4 (LTM4676) control,
active low
refer to current SC CPLD firmware for functionality
LTM2_ALERTDC-DC U3, pin E5
LTM_1V_IO0DC-DC U4, pin E4
LTM_1V_IO1DC-DC U4, pin F5
LTM_1V5_4V_IO0DC-DC U3, pin E4
LTM_1V5_4V_IO1DC-DC U3, pin F4

DDR3 SDRAM ECC SO-DIMM Socket

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anchorTable_OBP_SO_DIMM
titleDDR3 SODIMM socket I²C interface

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I²C InterfaceSchematic net namesConnected toI²C AddressNotes
DDR3 SODIMM, U2

'DDR3_SDA', pin 200
'DDR3_SCL', pin 202

SC CPLD U5, pin 42
SC CPLD U5, pin 43

module dependent-
Info

It is important to use SO-DIMMs which provide ECC functionality. SO-DIMMs without ECC are not compatible with this board.

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anchorTable_OBP_QSPI
titleQuad SPI interface signals and connections

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Signal NameQSPI Flash Memory U12 PinFPGA Pin
FLASH_QSPI_CSS, Pin 7Bank 14, Pin C23
FLASH_QSPI_D00DQ0, Pin 15Bank 14, Pin B24
FLASH_QSPI_D01DQ1, Pin 8Bank 14, Pin A25
FLASH_QSPI_D02DQ2, Pin 9Bank 14, Pin B22
FLASH_QSPI_D03DQ3, Pin 1Bank 14, Pin A22
FPGA_CFG_CCLKC, Pin 16Bank 0, Pin C8
Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

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anchorTable_OBP_SI5338A
titleProgrammable quad PLL clock generator inputs and outputs

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Si5338A Pin
Signal Name / Description
Connected toDirectionNote

IN1

-

not connectedInput

not used

IN2-GNDInputnot used

IN3

Reference input clock

U3, pin 3Input25.000000 MHz oscillator U14, Si8208AI

IN4

-GNDInputI2C slave device address LSB

IN5

-

not connectedInputnot used
IN6-GNDInputnot used
SCLPLL_SCLSC CPLD U5, pin 8Input / Output

I²C interface muxed to FPGA

Slave address: 0x70.

SDAPLL_SDASC CPLD U5, pin 2Input / Output

CLK0A

CLK0_P

U6, G24Output

Clock to PL bank 14

CLK0BCLK0_NU6, F24
CLK1AMGTCLK_5338_PU6, H6Output

Clock to MGT bank 115,
AC decoupled

CLK1BMGTCLK_5338_NU6, H5
CLK2ACLK1_PU6, G22OutputClock to PL bank 14
CLK2BCLK1_NU6, F23
CLK3A

CLK2_P

U6, D23OutputClock to PL bank 14
CLK3BCLK2_NU6, D24

Oscillators

The FPGA module has following reference clocking sources provided by on-board oscillators and FMC connector J2:

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anchorTable_OBP_OSC
titleReference clock signals

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Clock SourceFrequencySignal Schematic NameClock DestinationNotes
U14, SiT8208AI25.000000 MHzCLKSi5338A PLL U13, pin 3 (IN3)-
U1, DSC1123DL5200.0000 MHzDDR3_CLK_PFPGA bank 33, pin AB11

Enable by SC CPLD U5, pin 30

Signal: '200MHzCLK_EN'

DDR3_CLK_NFPGA bank 33, pin AC11
FMC Connector J2-GBTCLK0_M2C_P, Pin J2-D4FPGA bank 116, pin D6reference clock to MGT bank 116
GBTCLK0_M2C_N, Pin J2-D5FPGA bank 116, pin D5
-GBTCLK1_M2C_P, Pin J2-B20FPGA bank 116, pin F6reference clock to MGT bank 116
GBTCLK1_M2C_N, Pin J2-B21FPGA bank 116, pin F5
-CLK0_M2C_P, Pin J2-H4FPGA bank 15, pin H17reference clock to PL bank 15
CLK0_M2C_N, Pin J2-H5FPGA bank 15, pin H18
-CLK1_M2C_P, Pin J2-G2FPGA bank 15, pin G17reference clock to PL bank 15
CLK1_M2C_N, Pin J2-G3FPGA bank 15, pin G18
-CLK2_BIDIR_P, Pin J2-K4FPGA bank 13, pin P23reference clock to PL bank 13
bidirectional clock line
CLK2_BIDIR_N, Pin J2-K5FPGA bank 13, pin N23
-CLK3_BIDIR_P, Pin J2-J2FPGA bank 13, pin R22reference clock to PL bank 13
bidirectional clock line
CLK3_BIDIR_N, Pin J2-J3FPGA bank 13, pin R23

On-board LEDs

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anchorTable_OBP_LEDs
titleOn-board LEDs description

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LEDColorSignal Schematic nameConnected toDescription and Notes
D1GreenFPGA_LED1_VTFPGA bank 13, pin K25

LEDs D1 to D10 are available to user.

LED voltages are translated from FPGA bank 13 and 14
VCCO voltage FMC_VADJ to 3V3.

D2GreenFPGA_LED2_VTFPGA bank 13, pin K26
D3GreenFPGA_LED3_VTFPGA bank 13, pin P26
D4GreenFPGA_LED4_VTFPGA bank 13, pin R26
D5GreenFPGA_LED5_VTFPGA bank 13, pin N16
D6GreenFPGA_LED6_VTFPGA bank 14, pin J26
D7GreenFPGA_LED7_VTFPGA bank 14, pin H26
D8GreenFPGA_LED8_VTFPGA bank 14, pin E26
D9GreenFPGA_LED9_VTFPGA bank 14, pin A24
D10GreenFPGA_LED10_VTFPGA bank 15, pin F19
D11GreenLED1System Controller CPLD, bank 0, pin 76refer to current CPLD firmware for LED functionality

Configuration DIP-switch

There is one 4-bit DIP-witches S1 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

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anchorTable_OBP_DIP
titleDIP-switch S1 functionality description

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DIP-switch S3Signal Schematic NameConnected toFunctionalityNotes
S1-1JTAG_ENSC CPLD U5, bank 1, pin 82enables JTAG interface of SC CPLD U5 in ON-positionSC CPLD programmable through JTAG header J8
S1-2VID0_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 71set 3bit code to adjust FMC_VADJ voltage

The FMC_VADJ voltage is provided by DCDC U7 EN5365QI,

the voltage can be adjusted from 0.8V to 3.3V in 7 steps:

Set DIP-switches as  bit pattern "S1-4 | S1-3 | S1-2:  FMC_VADJ":

0 | 0 | 0 :   3.3V
0 | 0 | 1 :   2.5V
0 | 1 | 0 :   1.8V
0 | 1 | 1 :   1.5V
1 | 0 | 0 :   1.25V
1 | 0 | 1 :   1.2V
1 | 1 | 0 :   0.8V
1 | 1 | 1 :   Reserved

S1-3VID1_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 63
S1-4VID2_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 62

Push Buttons

There is one push buttons available to the user connected to the SC CPLD U5:

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anchorTable_PWR_CONSUMPTION
titleTypical power consumption

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Power InputTypical Current
12V VINTBD*

 * TBD - To Be Determined soon with reference design setup.

It is recommended to connect the ATX connector J5 to a 12V power supply source with minimum current capability of 6A to provide a sufficient power source to the board. Only one power source is needed at the same time, the system disconnects automatically PCIe power supply from PCIe edge connector J1 if the board is powered by the ATX connector J5.

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Scroll Title
anchorTable_PWR_BV
titleBoard I/O bank voltages

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BankSchematic NameVoltageRangeNotes
01V81.8V-Config bank 0 fixed to 1.8V
12FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
13FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
141V81.8VHR: 1.2V to 3.3VPL bank 14 fixed to 1.8V
15FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
16VIO_B_FMCuserHR: 1.2V to 3.3VPL bank 16 fixed to 1.8V
321V51.5VHP: 1.2V to 1.8VDDR3 memory interface
331V51.5VHP: 1.2V to 1.8VDDR3 memory interface
341V51.5VHP: 1.2V to 1.8VDDR3 memory interface

115

116

MGTAVCC_FPGA

MGTVCCAUX_FPGA

MGTAVTT_FPGA

1.0V

1.8V

1.2V

MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTX transceiver units

Power Rails

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anchorTable_PWR_PR
titleBoard power rails

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Connector / PinVoltageDirectionNotes
J4, pin 212VOutput4-wire PWM fan connector supply voltage
J6, pin 25VOutputCooling fan M1 supply voltage
J8, pin 63V3OutputVCCIO CPLD JTAG
J9, pin 21V8OutputVCCIO FPGA JTAG
J2, pin C35 / C3712VOutputFMC supply voltage
J2, pin D323V3OutputVCCIO FMC
J2, pin D36 / D38 / D39 / D403V3FMCOutputVCCIO FMC
J2, pin H1VREF_A_M2CInputVREF voltage for bank 13 / 15
J2, pin K1VREF_B_M2CInputVREF voltage for bank 16
J2, pin J39 / J40VIO_B_FMCInputPL I/O voltage bank 16 (VCCO)
J2, pin H40 / G39 / F40 / E39FMC_VADJOutputPL I/O voltage bank 12 / 13 / 15 (VCCO)
J1, pin B1 / B2 / B3 / A2 / A312V_input_BInput12V main power supply from PCIe connector
J5, pin 1 / 2 / 312V_input_AInputMain power supply connector

Technical Specifications

Absolute Maximum Ratings

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Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.320

V

TPS6217 datasheet

Note: voltage limitations are not valid for connected FMC module and/or FPGA FAN

Supply voltage for HR I/O banks (VCCO)

-0.500

3.600

VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)

-0.500

2.000VXilinx datasheet DS182
I/O input voltage for HR I/O banks

-0.500

VCCO + 0.500

VXilinx datasheet DS182

I/O input voltage for HP I/O banks

-0.500

VCCO + 0.500

VXilinx datasheet DS182
Reference Voltage pin (VREF)-0.5002VXilinx datasheet DS182
Differential input voltage-0.52.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.53.75VLattice MachXO2 Family datasheet
GTX transceiver reference clocks absolute input voltage-0.5001.320VXilinx datasheet DS182

GTX transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage

-0.500

1.260

VXilinx datasheet DS182
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10-0.35.5VLTM4676A datasheet

Storage temperature

-40

+100

°C

SML-P11 LED datasheet
Note
Assembly variants for higher storage temperature range are available on request.

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ParameterMinMaxUnitsReference Document
VIN supply voltage11.412.6V12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)1.140

3.465

VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)

1.140

1.890

VXilinx datasheet DS182

I/O input voltage for HR I/O banks

-0.500

VCCO + 0.20VXilinx datasheet DS182
I/O input voltage for HP I/O banks-0.500VCCO + 0.20VXilinx datasheet DS182
Differential input voltage-0.22.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.33.6VLattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J1003.3VVLTM4676A datasheet

Board Operating Temperature Range 1), 2)

-4085°C

board operating temperature range limited by FPGA SoC and on-board peripherals


1) Temperature range may vary depending on assembly options

2) The operating temperature range of the FPGA soC and on-board peripherals are junction and also ambient operating temperature ranges

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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Trenz shop TEF1001 overview page
English pageGerman page

Revision History

Hardware Revision History

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DateRevision

Notes

PCNDocumentation Link
-02current available board revision--
-

01

First production release

PCN-20180524 TEF1001-01TEF1001-01



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