Page History
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- Power Management
- Reset Management
- FMC JTAG
- LED Control
- FAN Control (FPGA)
- FAN Control (FMC
- I2C MUX
Firmware Revision and supported PCB Revision
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| Name / opt. VHD Name | Direction | Pin | Description | Connection changes compared to REV01 | |
|---|---|---|---|---|---|
| 200MHZCLK_EN | out | 30 | Enable 200MHz Osc. | ||
| BUTTON | in | 77 | Reset Button | ||
| CPLD_JTAG_TCK | in | 91not accessible as IO | optional FMC JTAG | ||
| CPLD_JTAG_TDI | in | 94not accessible as IO | optional FMC JTAG | ||
| CPLD_JTAG_TDO | out | 95not accessible as IO | optional FMC JTAG | ||
| CPLD_JTAG_TMS | in | 90not accessible as IO | optional FMC JTAG | ||
| DDR3_SCL | inout | 43 | I2C connected to FPGA | ||
| DDR3_SDA | inout | 42 | I2C connected to FPGA | ||
| DONE | in | 18 | FPGA Done | ||
| EN_1V8 | out | 58 | Power Enable | ||
| EN_3V3FMC | out | 60 | Power Enable | ||
| EN_FMC_VADJ | out | 51 | Power Enable | ||
| F1PWM | out | 98 | FAN | ||
| F1SENSE | in | 99 | FAN / currently_not_used | ||
| FEX_DIR | 19 | / currently_not_used | |||
| FEX0 | out | 12 | PERST from PCIe slot | ||
| FEX1 | 15 | / currently_not_used | |||
| FEX10 | 4 | / currently_not_used | |||
| FEX11 | in | 10 | User LED | ||
| FEX2 | 13 | / currently_not_used | |||
| FEX3 | 9 | / currently_not_used | |||
| FEX4 | 3 | / currently_not_used | |||
| FEX5 | 7 | / currently_not_used | |||
| FEX6 | 24 | / currently_not_used | |||
| FEX7 | 17 | / currently_not_used | |||
| FEX8 | 21 | / currently_not_used | |||
| FEX9 | 25 | / currently_not_used | |||
| FAN_FMC_EN | out | 78 | FMC FAN Enable | not connected on REV01 | |
| FMC_PG_C2M | 69 | / currently_not_used | |||
| FMC_PG_M2C | 68 | / currently_not_used | |||
| FMC_PRSNT | in | 40 | FMC Present (inverted FMC_PRSNT_M2C_L ) | 70 | not connected on REV01 |
| N.C. | 70 | Not Connected | FMC_PRSNT_M2C_L on REV01 | / currently_not_used||
| FMC_SCL | 49 | I2C connected to FPGA | |||
| FMC_SDA | 48 | I2C connected to FPGA | |||
| FMC_TCK | 27 | / currently_not_used | |||
| FMC_TDI | 31 | / currently_not_used | |||
| FMC_TDO | 32 | / currently_not_used | |||
| FMC_TMS | 28 | / currently_not_used | |||
| FMC_TRST | 36 | / currently_not_used | |||
| FPGA_IIC_OE | 14 | I2C FPGA | |||
| FPGA_IIC_SCL | 1 | I2C FPGA | |||
| FPGA_IIC_SDA | 16 | I2C FPGA | |||
| JTAG_EN | in | 82 | JTAG ENABLE over DIP S1-1 | constant high on REV01 | |
| LED1 | out | 76 | Status LED D1 (green) | ||
| LTM_1V_IO0 | 86 | Power Good | |||
| LTM_1V_IO1 | 88 | Power Good | |||
| LTM_1V5_4V_IO0 | 85 | Power Good | |||
| LTM_1V5_4V_IO1 | 83 | Power Good | |||
| LTM_1V5_RUN | 74 | / currently_not_used | |||
| LTM_4V_RUN | 75 | / currently_not_used | |||
| LTM_SCL | 67 | I2C connected to FPGA | |||
| LTM_SDA | 66 | I2C connected to FPGA | |||
| LTM1_ALERT | 65 | / currently_not_used | |||
| LTM2_ALERT | 64 | / currently_not_used | |||
| PCIE_RSTB | in | 37 | PERST from PCIe card edge connector | ||
| PG_1V8 | in | 59 | Power Good | ||
| PG_3V3 | in | 61 | Power Good | ||
| PG_FMC_VADJ | in | 52 | Power Good | ||
| PLL_SCL | inout | 2 | I2C SI5338 | ||
| PLL_SDA | inout | 8 | I2C SI5338 | ||
| PROGRAM_B | out | 20 | FPGA PROG_B | ||
| VID0_FMC_VADJ | out | 53 | FMC EN5365QI power selection pin | ||
| VID0_FMC_VADJ_CTRL | in | 71 | Power pin pre-selection for FMC VADJ through DIP SW S1-2. CPLD decides. | not connected on REV01 | |
| VID1_FMC_VADJ | out | 54 | FMC EN5365QI power selection pin | ||
| VID1_FMC_VADJ_CTRL | in | 63 | Power pin pre-selection for FMC VADJ through DIP SW S1-3. CPLD decides. | not connected on REV01 | |
| VID2_FMC_VADJ | out | 57 | FMC EN5365QI power selection pin | ||
| VID2_FMC_VADJ_CTRL | in | 62 | Power pin pre-selection for FMC VADJ through DIP SW S1-4. CPLD decides. | not connected on REV01 |
Functional Description
JTAG
CPLD JTAG is always enabledselectable with DIP S1-1. (ON FMC, OFF CPLD).
FMC JTAG is accessible with J9 JTAG Pinheader on PCB REV02 and newer only.
Power
Power sequence on will be executed over 4 States:
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State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to selectable via DIP S1-2...4.
| S1-4 | S1-3 | S1-2 | Voltage |
|---|---|---|---|
| OFF | OFF | OFF | 3.3V |
| OFF | OFF | ON | 2.5V |
| OFF | ON | OFF | 1.9V |
| OFF | ON | ON | 1.5V |
| ON | OFF | OFF | 1.25V |
| ON | OFF | ON | 1.2V |
Note on PCB REV01 it's fix 1.8V.
Reset
PROGRAM_B is controlled by push button after power up sequencing is ready.
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| Register Address | Name | Description |
|---|---|---|
| 0 | FAN CTRL | FAN Control register |
| 1 | FAN1 RPS | FAN1 Revolutions per second |
FAN FMC
Is enabled/disabled with FMC preset signal (PCB REV02 only).
Button
Button is debounced and controls PROG_B signal from FPGA.
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Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV02 to REV03
- FMC JTAG access over CPLD Programmer (not accessible on PCB REV01)
- DIP VADJ (not usable on PCB REV01)
- FMC FAN EN/DIS over FMC_PRSNT (not usable on PCB REV01)
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
- I2C for SI5338, LTM, FMC, SODIMM
- Add FAN Control over I2C
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV03 | REV02 |
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| v.1 | REV02 | REV01 |
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| 2017-08-06 | v.1 | REV01 | REV01 | John Hartfiel |
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| 2017-05-29 | v.1 | --- |
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| All |
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