Versions Compared

Old Version 4

changes.mady.by.user Pedram Babakhani

Saved on

compared with

New Version Current

changes.mady.by.user Thomas Dück

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Page properties
hiddentrue
idComments

Template Revision 272.7

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

Page properties
hiddentrue
idComments

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        style
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        widthssortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


...

Page properties
hiddentrue
idComments

Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... TEI0006 is an industrial - grade ... module ... based on Xilinx ...based on Intel® Cyclone 10 GX. Intel® Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.

Refer to http://trenz.org/tec0850tei0006-info for the current online version of this manual and other available documentation.

...

Page properties
hiddentrue
idComments

Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • ...
  • ....
  • ....

Block Diagram

...

hiddentrue
idComments

add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

  • Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
    • Package: FBGA-780
    • Speed Grade: 5 (Fastest)
    • Temperature: -40°C to 100°C
    • Package compatible device 10CX150 and 10CX105 as assembly variant on request possible
  • 2x SDRAM DDR3L Memory IC 8 Gbit (1 GByte), Half rate: 533 MHz; Quarter rate: max. 800 MHz
  • 2x SPI Flash, 1 Gbit (128 MByte)
  • 1x Gigabit Ethernet
  • 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/Clock Multiplier
  • Intel® MAX 10 as System Controller (CPLD)
  • 2 Kbit EEPROM Memory

  • 4x User LED 

  • I/O interfaces: 226/94/46 (IOs/DIFF. Pairs/LVDS Pairs)
  • 12 x 12.5Gbps Transceiver

  • Board to Board (B2B) Connection: Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors

  • 5 V Power Supply

  • Dimension: 80m x 60m

Block Diagram

Page properties
hiddentrue
idComments

add drawIO object here.

...

anchorFigure_OV_BD
titleTExxxx block diagram

...

Scroll Only

Image Removed

Main Components

Page properties
hiddentrue
idComments

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below

    Note

    For more information regarding how to add board photoesdraw a diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorFigure_OV_BD
    titleTExxxx main componentsTEI0006 block diagram


    Scroll Ignore
    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lbox
    true
    false
    revision
    1
    24
    diagramNameTEI0006_OV_
    MC
    BD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth
    641
    639



    Scroll Only

    Image Removed

    1. ...
    2. ...
    3. ...

    ...

    Image Added


    Main Components

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty

    Scroll Title
    anchorTable_OV_IDS
    titleInitial delivery state of programmable devices on the module
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    Content

    Notes

    Quad SPI Flash

    		EEPROMDDR3 SDRAMSystem Controller CPLD

    Configuration Signals

    Page properties
    hiddentrue
    idComments
    • Overview of Boot Mode, Reset, Enables.
    • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below


    Note

    For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



    Scroll Title
    anchorFigure_OV_BD
    titleTEI0006 main components


    Scroll Ignore

    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxfalse
    revision8
    diagramNameTEI0006_OV_MC
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth641


    Scroll Only

    Image Added



    1. Intel® MAX 10, U18
    2. DC/DC convertor, U4...11
    3. SDRAM DDR3 Memory, U12 - U13
    4. User LEDs, D1...4
    5. Ethernet Transceiver, U2
    6. SPI Flash Memory, U1 - U3
    7. Intel® Cyclone 10 GX, U23
    8. EEPROM, U64
    9. Buffer, U16
    10. 10-Channel Clock Multiplier, U14
    11. CryptoAuthentication Device (optional), U19

    Initial Delivery State

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty


    Scroll Title
    anchorTable_OV_IDS
    titleInitial delivery state of programmable devices on the module
    Scroll Title
    anchorTable_OV_BP
    titleBoot process.
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    MODE Signal State

    		Boot Mode
    Scroll Title
    anchorTable_OV_RST
    titleReset process.

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    Signal

    Content

    		B2BI/ONote

    ...

    Notes

    Intel® MAX 10ProgrammedSee CPLD Firmware

    Quad SPI Flash

    		Not Programmed


    EEPROMProgrammed

    Ethernet MAC

    DDR3 SDRAMNot Programmed



    Configuration Signals

    Page properties
    hiddentrue
    idComments

    Notes :

    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    Board to Board (B2B) I/Os

    FPGA bank number and number of I/O signals connected to the B2B connector:

    • Overview of Boot Mode, Reset, Enables.

    The TEI0006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.

    Scroll Title
    anchorTable_OV_BP
    titleBoot process.
    Scroll Title
    anchorTable_SIP_B2B
    titleGeneral PL I/O to B2B connectors information

    Scroll Table Layout
    style
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    widthssortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

    ...

    JTAG access to the TExxxx SoM through B2B connector JMX.

    ...

    anchorTable_SIP_JTG
    titleJTAG pins connection

    MODE Signal State

    		MSEL2MSEL1MSEL0Boot Mode

    MSEL[2:0]

    		010

    AS / Fast

    011

    AS / Standard

    000PS and FPP / Fast
    001PS and FPP / Standard


    By tying the CONF_DONE, NSTATUS, and NCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the NSTATUS pin, it resets the chain by pulling its NSTATUS pin low.

    Scroll Title
    anchorTable_OV_BP_CS
    titleConfiguration signals.

    ...

    JTAG Signal

    ...

    B2B Connector

    ...

    MIO Pins

    you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

    Example:

    Page properties
    hiddentrue
    idComments
    MIO PinConnected toB2BNotes
    MIO12...14

    SPI_CS , SPI_DQ0... SPI_DQ3

    SPI_SCK

    		J2QSPI
    Scroll Title
    anchorTable_OBP_MIOs
    titleMIOs pins

    Scroll Table Layout
    style
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    widthssortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    MIO Pin
    SignalsConnected to
    B2B
    Description
    		Notes

    ...

    Note
    NCONFIG1.8VConfiguration triggerFrom U18 (Intel MAX 10) - Bank 3
    CONF_DONE1.8VConfiguration done To U18 (Intel MAX 10) - Bank 3
    NSTATUS1.8VConfiguration status To U18 (Intel MAX 10) - Bank 3
    DCLKU1Configuration clock 

    To U1 (Flash Memory)

    From U18 (Intel MAX 10) - Bank 3

    AS_DATA0...3U1Configuration dataFrom U1 (Flash Memory)
    Page properties
    hiddentrue
    idComments

    Notes :

    • add subsection for every component which is important for design, for example:
      • Two 100 Mbit Ethernet Transciever PHY
      • USB PHY
      • Programmable Clock Generator
      • Oscillators
      • eMMCs
      • RTC
      • FTDI
      • ...
      • DIP-Switches
      • Buttons
      • LEDs
    Page properties
    hiddentrue
    idComments

    Notes :

    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection



    Scroll Title
    anchorTable_OV_OBPRST
    titleOn board peripheralsReset process.

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Chip/InterfaceDesignatorNotes

    ...

    Signal

    		B2BConnected toNote

    PERST

    		J2-99Bank A2


    Signals, Interfaces and Pins

    Page properties
    hiddentrue
    idComments

    Notes :

    Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

    Scroll Title
    anchorTable_OBP_SPI
    titleQuad SPI interface MIOs and pins
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    MIO PinSchematicU?? PinNotes

    ...

    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    Board to Board (B2B) I/Os

    FPGA bank number and number of I/O signals connected to the B2B connector:

    Scroll Title
    anchorTable_SIP_B2B
    titleGeneral PL I/O to B2B connectors information
    Scroll Title
    anchorTable_OBP_RTC
    titleI2C interface MIOs and pins

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    MIO PinSchematicU? PinNotes
    Scroll Title
    anchorTable_OBP_I2C_RTC
    titleI2C Address for RTC
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    MIO PinI2C AddressDesignatorNotes

    ...

    anchorTable_OBP_EEP
    titleI2C EEPROM interface MIOs and pins

    FPGAFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

    Intel Cyclone 10 GX

    Bank 1C

    J3

    12 Diff pair

    0.95V

    GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P

    Bank 1D

    J3

    12 Diff pair

    0.95V

    GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P

    Bank 2A

    J2

    2 Single ended

    1.8V

    PERST, CLKUSR

    Bank 2J

    J2

    46 Single ended (23 Diff pair)

    VCCIO2J


    Bank 2K

    J1

    46 Single ended (23 Diff pair)

    VCCIO2K


    Bank 2L

    J1

    48 Single ended (24 Diff pair)

    VADJ up to 3 V


    Bank 3A

    -

    -

    1.35V

    VDD_DDR

    Bank 3B

    -

    -

    1.35V

    VDD_DDR

    Intel Max 10

    Bank 1A

    J2

    8 Single ended

    3.3V


    Bank 1B

    J2

    5 Single ended

    3.3V


    Bank 2

    J3

    1 Single ended

    1.8VIO


    Bank 3

    -

    -

    1.8VIO


    Bank 5

    J2

    3 Single ended

    3.3V


    Bank 6

    J2

    2 Single ended

    3.3V


    Bank 8

    J2

    23 Single ended

    3.3V




    JTAG Interface

    JTAG access to the TEI0006 SoM is through B2B connector J2. JTAGEN is pulled up to 3.3V and after power on, JTAG for MAX 10 CPLD is enabled. JTAG port of Cyclon 10 GX device is routed to MAX10 CPLD IOs. The default Firmware connects the JTAG port of the Cyclon 10 GX to the IO pins of the JTAG port in user IO mode. Setting JTAGEN to GND enables JTAG for the Cyclon 10 GX device.

    ...

    anchorTable_OBP_I2C_EEPROM
    titleI2C address for EEPROM

    ...

    LEDs

    Scroll Title
    anchorTable_OBPSIP_LEDJTG
    titleOn-board LEDsJTAG pins connection

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SchematicColorConnected toActive LevelNote

    ...

    JTAG Signal

    B2B Connector

    		Note
    TMSJ2-160
    TDIJ2-159
    TDOJ2-158
    TCK

    J2-157


    JTAGENJ2-105Pulled up to 3.3V.


    MIO Pins

    Page properties
    hiddentrue
    idComments

    Notes :

    Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

    The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

    • Part number: 
    • Supply voltage:
    • Speed: 
    • NOR Flash
    • Temperature: 

    you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

    Example:

    MIO PinConnected toB2BNotes
    MIO12...14

    SPI_CS , SPI_DQ0... SPI_DQ3

    SPI_SCK

    		J2QSPI

    ...



    Scroll Title
    anchorTable_OBP_ETHMIOs
    titleEthernet PHY to Zynq SoC connectionsMIOs pins

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    BankSignal NameETH1ETH2Signal Description

    CAN Transceiver

    ...

    anchorTable_OBP_CAN
    titleCAN Tranciever interface MIOs

    ...

    MIO PinConnected toB2BNotes
    MAX_IO1...20, 22U18 (Intel MAX 10) - Bank 8J2
    MAX_IO23, 25, 26U18 (Intel MAX 10) - Bank 5
    		J2



    On-board Peripherals

    Page properties
    hiddentrue
    idComments

    Notes :

    • add subsection for every component which is important for design, for example:
      • Two 100 Mbit Ethernet Transciever PHY
      • USB PHY
      • Programmable Clock Generator
      • Oscillators
      • eMMCs
      • RTC
      • FTDI
      • ...
      • DIP-Switches
      • Buttons
      • LEDs


    Page properties
    hiddentrue
    idComments

    Notes :

    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

    ...


    Scroll Title
    anchorTable_OBP_CLK
    titleOsillatorsOn board peripherals

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Chip/InterfaceDesignatorNotes
    		DescriptionFrequencyNoteMHzMHzKHz

    Power and Power-On Sequence

    ...

    hiddentrue
    idComments

    In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

    • Power on-sequence
    • Power distribution
    • Voltage monitoring circuit
    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

    QSPI Flash Memory

    		U1 - U3U1- AS configuration
    EEPROMU64
    DDR3 SDRAM MemoryU12 - U13
    Ethernet PHYU2

    Intel Max 10U18System controller

    User LEDs

    		D1...4D1 (Red), D2...4 (Green)
    OscillatorsU14, U15, U17, U21, Y1

    CryptoAuthentication DeviceU19optional


    QSPI Flash Memory

    Page properties
    hiddentrue
    idComments

    Notes :

    Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

    The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

    Power Supply

    Power supply with minimum current capability of xx A for system startup is recommended.

    Power Consumption

    ...

    anchorTable_PWR_PC
    titlePower Consumption

    ...

    * TBD - To Be Determined

    ...

    Scroll Title
    anchorFigureTable_PWROBP_PDSPI
    titlePower DistributionQuad SPI interface MIOs and pins

    scroll-

    ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Power-On Sequence

    ...

    anchorFigure_PWR_PS
    titlePower Sequency
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Voltage Monitor Circuit

    ...

    anchorFigure_PWR_VMC
    titleVoltage Monitor Circuit

    tablelayout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DesignatorSchematicConnected toNotes
    U1



    		NCSOCSS Bank (Configuration Bank)Used when you are not configuring using AS
    DCKDCLKAS Configuration Clock
    AS_DATA0CSS Bank (Configuration Bank)
    AS_DATA1CSS Bank (Configuration Bank)
    AS_DATA2CSS Bank (Configuration Bank)
    AS_DATA3CSS Bank (Configuration Bank)
    U3QSPI_CSBank 2A
    QSPI_CKBank 2A
    QSPI_DATA0Bank 2A
    QSPI_DATA1Bank 2A
    QSPI_DATA2Bank 2A
    QSPI_DATA3Bank 2A


    EEPROM

    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Power Rails

    ...

    anchorTable_PWR_PR
    titleModule power rails.

    ...

    B2B Connector

    JM1 Pin

    ...

    B2B Connector

    JM2 Pin

    ...

    B2B Connector

    JM3 Pin

    ...

    Voltage
    Scroll Title
    anchorTable_PWROBP_BVEEP
    titleZynq SoC bank voltages.I2C EEPROM interface MIOs and pins

    Scroll Table Layout
    style
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    widthssortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Schematic

    Bank          

    		Schematic Name

    U64 EEPROM Pin

    		B2B

    U18 Intel Max 10 Pin

    		Notes

    ...

    hiddentrue
    idComments

    ...

    I2C_SCLSCLJ3-135Bank 2 - K2
    I2C_SDASDAJ3-137Bank 2 - L2



    Scroll Title
    anchorTable_OBP_I2C_EEPROM
    titleI2C address for EEPROM

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault

    use "include page" macro and link to the general B2B connector page of the module series,

    ...

    ? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

    • 3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

      Operating Temperature: -??°C ~ ??°C
      Current Rating: ??A per ContactNumber of Positions: ??
      Number of Rows: ??

    Technical Specifications

    Absolute Maximum Ratings

    Scroll Title
    anchorTable_TS_AMR
    titlePS absolute maximum ratings

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Symbols
    Pins
    Description
    I2C Address
    Min
    Designator
    		MaxUnitVVVVVVVV

    Recommended Operating Conditions

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    Notes
    I2C_SCL, I2C_SDA0x53U64


    DDR3 SDRAM

    Page properties
    hiddentrue
    idComments

    Notes :

    Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

    The TEI0006 SoM has two 1 GByte volatile DDR3 SDRAM IC provided by Integrated Silicon Solution Inc for storing user application code and data.

    • Part number: IS43TR16512BL
    • Supply voltage: 1.35 V
    • Speed: Half rate: 533 MHz; Quarter rate: max. 800 MHz
    • Temperature: -40 °C to 95 °C

    Ethernet PHY

    Scroll Title
    anchorTable_OBP_ETH
    titleEthernet PHY to Intel Cyclone 10 GX SoC connections
    Scroll Title
    anchorTable_TS_ROC
    titleRecommended operating conditions.

    Scroll Table Layout
    widths
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefaultstyle
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Parameter
    Signal Name
    Min
    Connected to
    Max
    B2B
    		UnitsReference DocumentVSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.

    Physical Dimensions

    • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: ? mm.

    PCB thickness: ?? mm.

    ...

    hiddentrue
    idComments

    In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

    Signal Description

    PHY1_MDI0_P

    PHY1_MDI0_N

    -

    -

    J2-93

    J2-91


    PHY1_MDI1_P

    PHY1_MDI1_N

    -

    -

    J2-87

    J2-85


    PHY1_MDI2_P

    PHY1_MDI2_N

    -

    -

    J2-81

    J2-79


    PHY1_MDI3_P

    PHY1_MDI3_N

    -

    -

    J2-75

    J2-73


    ETH1_RSTU23, Bank 2A-Pulled-up to DVDDH Voltage.
    ETH1_MDCU23, Bank 2A-Pulled-up to DVDDH Voltage.
    ETH1_MDIOU23, Bank 2A-Pulled-up to DVDDH Voltage.
    ETH1_TXD0...7U23, Bank 2A-8 bit Transfer
    ETH1_RXD0...7U23, Bank 2A-8 bit Receive
    ETH1_GTXCKU23, Bank 2A-
    ETH1_TXCLKU23, Bank 2A-
    ETH1_TXENU23, Bank 2A-
    ETH1_TXERU23, Bank 2A-
    ETH1_RXCKU23, Bank 2A-Pulled-down to GND.
    ETH1_RXDVU23, Bank 2A-Pulled-down to GND.
    PHY1_INT--Pulled-up to DVDDH Voltage.
    PHY1_LED1U18, Bank 2

    -

    		Pulled-up to DVDDH Voltage.
    PHY1_LED2U18, Bank 2-Pulled-down to GND.
    ETH1_CRSU23, Bank 2A-
    ETH1_XTAL_INETH_CLKIN-From U21 (25 MHz Oscillator)


    Intel MAX 10

    The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM. 

    Scroll Title
    anchorTable_SIP_MAX10
    titleIntel MAX 10 banks information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Intel Max 10 BankSignalsConnected to DescriptionNotes
    Bank 1AAIN0...7B2B- J2

    Bank 1BTCK, TDO, TMS, TDI, JTAGENB2B- J2

    Bank 2

    PHY1_LED1

    PHY1_LED2

    Ethernet PHY, U2

    Ethernet PHY, U2

    Ethernet LED

    Ethernet LED

    Pulled-up to DVDDH.

    Pulled-down to GND.

    F_TCK, F_TDO, F_TDI, F_TMSIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 JTAG signals
    I2C_SDA, I2C_SCL

    EEPROM, U64

    B2B, J3 

    Programmable Oscillator, U14

    		I2C EEPROM signals
    PLL_RST

    Programmable Oscillator, U14

    		Oscillator reset signal
    Bank 3NSTATUS, NCONFIG, CONF_DONEIntel Cyclone 10 GX (U23) - Bank CSSIntel Cyclone 10 Configuration signals
    DCLK

    Intel Cyclone 10 GX (U23) - Bank CSS

    SPI Flash, U1

    Intel Cyclone 10

    Configuration clock from Flash memory


    MSEL0...1Intel Cyclone 10 GX (U23) - Bank CSS

    Intel Cyclone 10

    Configuration mode signals


    DEV_CLRN, INIT_DONEIntel Cyclone 10 GX (U23) - Bank 2A

    M10_IO0...4Intel Cyclone 10 GX (U23) - Bank 2A

    Bank 5

    		DIS_GROUP1...4N-Channel MOSFET, T1...4Fast Discharching
    MAX_IO23...26B2B, J2Intel MAX 10 GPIO

    PG_0.95V, EN_0.95V

    PG_1.8VIO, EN_1.8VIO

    Voltage Regulator, U7

    Voltage Regulator, U6

    		Power control signals
    Bank 6




    		M10_CLK25 MHz Oscillator, U21Intel MAX 10 Clock

    VADJ_VS0...2, VADJ_EN

    PG_1.35V, EN_1.35V

    PG_1.8V, EN_1.8V

    PG_VTT, EN_VTT

    PG_0V9, EN_0V9

    Voltage Regulator, U11

    Voltage Regulator, U8

    Voltage Regulator, U5

    Voltage Regulator, U9

    Voltage Regulator, U4

    		Power control signals
    PHY1_33LED1...2

    B2B, J2

    		Ethernet LED

    LED_FP_1

    LED_FP_2...4

    D1

    D2...4

    		User LEDs

    Red LED

    Green LED

    Bank 8

    M10_nSTATUS, M10_nCONFIG

    		B2B, J2Intel MAX 10 configuration signals
    MAX_IO1...20, 22B2B, J2Intel MAX 10 GPIO


    LEDs

    Scroll Title
    anchorTable_OBP_LED
    titleOn-board LEDs

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DesignatorColorConnected toActive LevelNote
    D1RedLED_FP_1Active high
    D2GreenLED_FP_2Active high
    D3GreenLED_FP_3Active high
    D4GreenLED_FP_4Active high


    Clock Sources

    The TEI0006 has one crystal, three MEMS oscillators and a programmable clock generator. 

    Scroll Title
    anchorTable_OBP_CLK
    titleOsillators

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DesignatorDescriptionFrequencyConnected to
    U21MEMS Oscillator25MHzU2 Ethernet
    U15MEMS Oscillator25MHzIN0 of U14
    U17MEMS Oscillator100 MHzU23, BANK2A USRCLK
    Y1Crystal Oscillator50MHzcrystal input of U14
    U14Programmable OscillatorVariable-



    Scroll Title
    anchorTable_OBP_CLK_PO
    titleProgrammable Oscillator connections

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SignalsClock TypeIn/ OutConnected toFrequencyNote

    IN0_P

    IN0_N

    Differential

    In

    In

    Oscillator, U15

    GND

    		25 MHz
    IN3 DifferentialInB2B, J3Variable

    XA, XB

    		Differential

    Oscillator, Y1

    		50 MHz

    CLK0

    		DifferentialOutIntel Cyclone 10 GX (U23)- Bank 2AUserDefault off

    CLK1...4

    		DifferentialOutB2B, J3UserDefault off
    REFCLK_EMIFPDifferentialOutIntel Cyclon 10 GX (U23)- Bank 3BUserDefault off
    CLK6...7DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1DUserDefault off
    CLK8...9DifferentialOutIntel Cyclon 10 GX (U23)- Bank 1CUserDefault off


    CryptoAuthentication

    ATECC608A (U19) is a CryptoAuthentication device connected to the I2C bus. This chip is optional, for further description see datasheet of manufacturer.

    Scroll Title
    anchorTable_OBP_EEP
    titleI2C Interface of CryptoAuthentication

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Schematic

    U19 Pin

    		B2B

    U18 Intel Max 10 Pin

    		Notes
    I2C_SCLSCLJ3-135Bank 2 - K2-
    I2C_SDASDAJ3-137Bank 2 - L2-


    Power and Power-On Sequence

    Page properties
    hiddentrue
    idComments

    In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

    • Power on-sequence
    • Power distribution
    • Voltage monitoring circuit


    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


    Power Supply

    Power supply with minimum current capability of 1 A for system startup is recommended.

    Power Consumption

    Scroll Title
    anchorTable_PWR_PC
    titlePower Consumption

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    FPGATypical Current
    Intel Cyclone 10 GXTBD*
    Intel MAX 10TBD*


    * TBD - To Be Determined

    Power Distribution Dependencies

    Scroll Title
    anchorFigure_PWR_PD
    titlePower Distribution


    Scroll Ignore

    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxfalse
    revision11
    diagramNameTEI0006_PWR_PD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth639


    Scroll Only

    Image Added


    Power-On Sequence

    Voltage regulators can be enabled through U18 (Intel MAX 10) - Bank 5 and 6.

    Scroll Title
    anchorFigure_PWR_PS
    titlePower Sequence


    Scroll Ignore
    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxfalse
    revision9
    diagramNameTEI0006_PWR_PS
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth639


    Scroll Only

    Image Added


    Power Rails

    Scroll Title
    anchorTable_PWR_PR
    titleModule power rails.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Power Rail Name

    B2B Connector

    J1 Pin

    B2B Connector

    J2 Pin

    B2B Connector

    J3 Pin

    		Voltage LevelDirectionNotes
    VIN145, 147,149, 151, 153, 155, 157, 159--5 VInput
    VCCIO2K53, 54--1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VInput
    VADJ140,142--adjustable between 1.8 V - 3.0 VOutputVoltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
    VCCIO2J-29,30-1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VInput

    3.3V

    		-149,150-3.3 VOutput
    1.8_VIO--1391.8 VOutput


    Bank Voltages

    Scroll Title
    anchorTable_PWR_BV
    titleSoC bank voltages.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    FPGAFPGA BankVoltage LevelNotes
    Intel Cyclone 10 GXBank 1C0.95 V

    Bank 1D

    		0.95 V
    Bank 2A1.8 V1.8VIO
    Bank 2J1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VVCCIO2J
    Bank 2K1.2 V, 1.25 V, 1.35 V, 1.5 V or 1.8 VVCCIO2K
    Bank 2Ladjustable between 1.8 V - 3.0 VVoltages according to EP53A8HQI datasheet
    Bank 3A1.35 VVDD_DDR
    Bank 3B1.35 VVDD_DDR
    Intel Max 10Bank 1A3.3 V
    Bank 1B3.3 V
    Bank 21.8 V1.8VIO
    Bank 31.8 V1.8VIO
    Bank 53.3V
    Bank 63.3V
    Bank 83.3V



    Board to Board Connectors

    Page properties
    hiddentrue
    idComments
    • This section is optional and only for modules.

    • use "include page" macro and link to the general B2B connector page of the module series,

      For example: 6 x 6 SoM LSHM B2B Connectors

      Include Page
      6 x 6 SoM LSHM B2B Connectors
      6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 8 SoM SS5/ST5 B2B Connectors
    6 x 8 SoM SS5/ST5 B2B Connectors

    Technical Specifications

    Absolute Maximum Ratings

    Scroll Title
    anchorTable_TS_AMR
    titleAbsolute maximum ratings

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SymbolsDescriptionMinMaxUnitNote
    VINPower supply-0.36.0VDetemined by U10.
    VCCIO - 3 V I/OI/O buffers power supply-0.54.10V

    Intel Cyclone 10 GX

    VCCIO - LVDS I/OI/O buffers power supply-0.52.46V

    Intel Cyclone 10 GX

    VADJAdjustable voltage-0.54.10V

    Intel Cyclone 10 GX

    T_STGStorage temperature-4085°C


    Recommended Operating Conditions

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    Scroll Title
    anchorTable_TS_ROC
    titleRecommended operating conditions.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    ParameterMinMaxUnitReference Document
    VIN5.05.0V
    VCCIO2.853.15VSee Intel Cyclone 10 GX datasheet.
    VADJ2.853.15VVCCIO


    Physical Dimensions

    • Module size: 60 mm × 80 mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: 5 mm.

    • PCB thickness: 1.7 mm
    Page properties
    hiddentrue
    idComments

    In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



    Scroll Title
    anchorFigure_TS_PD
    titlePhysical Dimension


    Scroll Ignore

    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxfalse
    revision3
    diagramNameTEI0006_TS_PD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth611


    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Image Added


    Currently Offered Variants 

    Page properties
    hiddentrue
    idComments

    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    if not available, set.


    Scroll Title
    anchorTable_VCP_SO
    titleTrenz Electronic Shop Overview

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Trenz shop TEI0006 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

    Scroll Title
    anchorTable_RH_HRH
    titleHardware Revision History

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DateRevisionChangesDocumentation Link
    202-12-2303
    • two input cloock signals on B2B connected directly to GXBL1C bank
    		REV03
    2019-09-1102
    • added 100MHz MEMS oscillator, remove CLKUSR signal from J2
    • replaced U21/U15 by SiT8008
    • added pull-up to M10_NSTATUS signal
    • added pull-up to M10_DEVCLRN, removed signal from J2
    • added optional CryptoAuthentication chip U19
    		REV02
    2018-08-1001-REV01


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    Scroll Title
    anchorFigure_RV_HRN
    titleBoard hardware revision number.


    Scroll Ignore

    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxfalse
    revision3
    diagramNameTEI0006_RV_RHN
    simpleViewerfalse
    width
    linksauto
    tbstyletop
    diagramWidth178


    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Image Added


    ...

    anchorFigure_TS_PD
    titlePhysical Dimension
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Currently Offered Variants 

    Page properties
    hiddentrue
    idComments

    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    if not available, set.

    ...

    anchorTable_VCP_SO
    titleTrenz Electronic Shop Overview

    ...

    Revision History

    Hardware Revision History

    List of online PCN ...Link

    ...

    anchorTable_RH_HRH
    titleHardware Revision History

    ...

    Document Change History

    Page properties
    hiddentrue
    idComments
    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following

      • Add new row below first

      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports

    ...

    Scroll Title
    anchorTable_RH_DCH
    titleDocument change history..

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DateRevisionContributorDescription

    Page info
    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    prefixv.
    typeFlat
    showVersionsfalse

    Page info
    infoTypeModified by
    typeFlat
    showVersionsfalse

    • corrected Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)
    2022-03-18v.85Vitali Tsiukala
    • Added Info about Gigabit Transceivers
    2021-06-07

    v.84

    		Martin Rohrmüller
    • corrected Physical Dimension figure
    • updated to REV03

    2020-01-17

    		v.82Martin Rohrmüller
    • updated to REV02

    2019-06-14

    		v.80Pedram Babakhani

    • Figures updated

    • Technical specifications updated

    2019-05-29

    		v.69Pedram Babakhani
    • initial release
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    change list
    DateRevisionContributorDescription

    Page info
    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    prefixv.
    typeFlat
    showVersionsfalse

    Page info
    infoTypeModified by
    typeFlat
    showVersionsfalse

    --

    all

    Page info
    infoTypeModified users
    typeFlat
    showVersionsfalse

    • --


    ...